From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64530CA0FED for ; Fri, 5 Sep 2025 06:21:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=F2gsAN+ZOtEADHYTxoJ3USR88ppxjOvinTQO3FRDJJA=; b=cyU7kyquQmLLpnFgyDn4o3M908 2YqhFLu8hfQ2xM/pYzQcXD5CwmkSSgyuv3XIP2kT0UITh+xDLUdDbyFgfpDAwxidtY4bIq4DY+KhJ GeNczU0TeocvN7TAllRx6RBLWh6UCSVFtykkwjEcS1N2mRs2vD0NsA4v2XQEojP5In9k0w2xbbiBd /CHSTPpDQea1MeHONdID+LIyiUl7QQ31ZzRYs+PlWSZeZUmnBYxix24k2cpaQkq9THeizeubqQezI RsFfauhgUn7V1D3wTTprxG9YqLKQ6TytrENHaw/k5BS5i74Z5tX1QLaFjV2jgPc5razmCEmBHDoT7 aMpDB1wg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uuPow-0000000HFRT-1fxh; Fri, 05 Sep 2025 06:21:14 +0000 Received: from lelvem-ot01.ext.ti.com ([198.47.23.234]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uuOrz-0000000Gx7h-1wJy for linux-arm-kernel@lists.infradead.org; Fri, 05 Sep 2025 05:20:20 +0000 Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5855KFv83246450; Fri, 5 Sep 2025 00:20:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757049615; bh=F2gsAN+ZOtEADHYTxoJ3USR88ppxjOvinTQO3FRDJJA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=tGQzT3HWuxWU/0NNEXhgiu3YAdv0ZfD9MeLO1Fbin3BcH3P8PZhTMX9A13OOiDqxl a5zGrpbWQvNthzk03Y0XXOaiRcUukuQiZ8sLqNrGrjrWaAoGhlt0A0Mm2HbNx2zl6+ M+J5KlEsNg9iVC0D7SmhQgMTidsd0rwHdZbWM1M8= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5855KFvP1405474 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 00:20:15 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 00:20:14 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 00:20:14 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5855Ioik220581; Fri, 5 Sep 2025 00:20:10 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Josua Mayer , Logan Bristol , Matthias Schiffer Subject: [PATCH v3 17/33] arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware Date: Fri, 5 Sep 2025 10:48:30 +0530 Message-ID: <20250905051846.1189612-18-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905051846.1189612-1-b-padhi@ti.com> References: <20250905051846.1189612-1-b-padhi@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250904_222019_591446_2750672D X-CRM114-Status: GOOD ( 11.22 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, only R5F remote processors are enabled for k3-am642-sr SoMs, whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Josua Mayer Cc: Logan Bristol Cc: Matthias Schiffer Requesting for review/test of this patch. v3: Changelog: 1. None Link to v2: https://lore.kernel.org/all/20250823160901.2177841-18-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 27/33] to [PATCH v2 17/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-28-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi index 81adae0a8e55..8cb61f831734 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -162,6 +162,24 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { reg = <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible = "shared-dma-pool"; + reg = <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg = <0x00 0xa5000000 0x00 0x00800000>; + alignment = <0x1000>; + no-map; + }; }; vdd_mmc0: regulator-vdd-mmc0 { @@ -291,6 +309,35 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; +&mailbox0_cluster6 { + status = "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx = <0 0 2>; + ti,mbox-tx = <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status = "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status = "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status = "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status = "reserved"; +}; + &main_i2c0 { pinctrl-names = "default"; pinctrl-0 = <&main_i2c0_default_pins>; @@ -524,6 +571,13 @@ &main_r5fss1_core1 { status = "okay"; }; +&mcu_m4fss { + mboxes = <&mailbox0_cluster6 &mbox_m4_0>; + memory-region = <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status = "okay"; +}; + /* SoC default UART console */ &main_uart0 { pinctrl-names = "default"; -- 2.34.1