From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 519B0CA1010 for ; Fri, 5 Sep 2025 05:53:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=8g1Me7nTagv+1RjX67dS+wwUjCxDSGo6MTr6Drmo76A=; b=PLjWe9UXvpqKB/ziRaDFwTbdMn XS8T5jnWLG54I803uegdaOIbYPUuQnRkkltmKMJsTLyxMxwq9VIz7HbrGRHKuvbssi4d3rJF62gRo gWV74C2NrLuySpzVGtUuw5Ac4JkGOJ/ipyq9Ujg7wOsGbhg9b5p/5mC/9xTQ9SNVoLiTnlOG9JKpp P/HlyPPryjmaD7SekjnN1w/iINTNu7ULFhzx3fT3zO7PuBKlu7O2TCFCW2Sd2Cy8kCvM3arE0v00E J4bAkED74OgP/ZkABvVZ9PM7GTcCgimMrweNKXkk32rwAbiycasTaSQjzuASD72JlLMM8OUwIZmoK Jf/sofKQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1uuPO8-0000000H7PR-3ASp; Fri, 05 Sep 2025 05:53:32 +0000 Received: from fllvem-ot04.ext.ti.com ([198.47.19.246]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1uuOrD-0000000Gwlf-2Rwk for linux-arm-kernel@lists.infradead.org; Fri, 05 Sep 2025 05:19:32 +0000 Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 5855JT9p3637200; Fri, 5 Sep 2025 00:19:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1757049569; bh=8g1Me7nTagv+1RjX67dS+wwUjCxDSGo6MTr6Drmo76A=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=s8Z3QNhBEBngIzfRSc0r70gU6yevQFuwPHJc9JnH26xF8/AaMq+W1ezeb0NYh7p7Z qx9puDc3LsnHZlLADN2amzdHB131ZMdhndz8T99bcbNOpVFgp/Ac4GLf8mTmifQGXD kRSzFf461ZbMja3qhxTnEd6P2nI8ZVyM4pWg6rco= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 5855JTp21404898 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Fri, 5 Sep 2025 00:19:29 -0500 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 00:19:28 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 00:19:28 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5855Ioia220581; Fri, 5 Sep 2025 00:19:24 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v3 07/33] arm64: dts: ti: k3-am62a: Enable remote processors at board level Date: Fri, 5 Sep 2025 10:48:20 +0530 Message-ID: <20250905051846.1189612-8-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250905051846.1189612-1-b-padhi@ti.com> References: <20250905051846.1189612-1-b-padhi@ti.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250904_221931_709922_5A28E66B X-CRM114-Status: GOOD ( 10.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Remote Processors defined in top-level AM62A SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Acked-by: Andrew Davis Tested-by: Judith Mendez --- v3: Changelog: 1. Carried A/B, T/B tags. Link to v2: https://lore.kernel.org/all/20250823160901.2177841-8-b-padhi@ti.com/ v2: Changelog: 1. Re-ordered patch from [PATCH 24/33] to [PATCH v2 07/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-25-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi | 2 ++ arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 1 + 5 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi index ee961ced7208..d22caa7c346b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -197,6 +197,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,sci = <&dmsc>; ti,sci-dev-id = <9>; ti,sci-proc-ids = <0x03 0xff>; + status = "disabled"; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi index 207ca00630d1..403adfbf7dce 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi @@ -406,6 +406,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster2 &mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &ospi0 { @@ -444,4 +445,5 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi index 9ef1c829a9df..23877dadc98d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -127,6 +127,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci = <&dmsc>; ti,sci-dev-id = <121>; ti,sci-proc-ids = <0x01 0xff>; + status = "disabled"; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts index bceead5e288e..03291862f07a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -870,6 +870,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0>, <&mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; }; &mcu_r5fss0 { @@ -880,6 +881,7 @@ &mcu_r5fss0_core0 { mboxes = <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; memory-region = <&mcu_r5fss0_core0_dma_memory_region>, <&mcu_r5fss0_core0_memory_region>; + status = "okay"; }; &c7x_0 { diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts index daea18b0bc61..d45fc42b03f3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -586,6 +586,7 @@ &wkup_r5fss0_core0 { mboxes = <&mailbox0_cluster0 &mbox_r5_0>; memory-region = <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status = "okay"; bootph-pre-ram; }; -- 2.34.1