* [PATCH v1 1/4] clk: rockchip: rk3368: fix SCLK_I2S_8CH_OUT flags
2025-09-05 13:23 [PATCH v1 0/4] clk/rockchip: Fix I2S 8CH mclk output for RK3368 WeiHao Li
@ 2025-09-05 13:23 ` WeiHao Li
2025-09-05 13:23 ` [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC WeiHao Li
` (2 subsequent siblings)
3 siblings, 0 replies; 10+ messages in thread
From: WeiHao Li @ 2025-09-05 13:23 UTC (permalink / raw)
To: heiko, robh
Cc: krzk+dt, conor+dt, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-clk, WeiHao Li
Clock SCLK_I2S_8CH_OUT has no capability to adjust clock frequency by
itself, add CLK_SET_RATE_PARENT flag to fix it.
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 95e6996adb..8159f643dc 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -371,7 +371,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
&rk3368_i2s_8ch_fracmux),
- COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
+ COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(6), 0, GFLAGS),
GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
--
2.39.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-05 13:23 [PATCH v1 0/4] clk/rockchip: Fix I2S 8CH mclk output for RK3368 WeiHao Li
2025-09-05 13:23 ` [PATCH v1 1/4] clk: rockchip: rk3368: fix SCLK_I2S_8CH_OUT flags WeiHao Li
@ 2025-09-05 13:23 ` WeiHao Li
2025-09-05 14:13 ` Krzysztof Kozlowski
2025-09-05 13:23 ` [PATCH v1 3/4] clk: rockchip: rk3368: use clock ids " WeiHao Li
2025-09-05 13:23 ` [PATCH v1 4/4] arm64: dts: rockchip: Assign I2S 8 channel clock for rk3368 WeiHao Li
3 siblings, 1 reply; 10+ messages in thread
From: WeiHao Li @ 2025-09-05 13:23 UTC (permalink / raw)
To: heiko, robh
Cc: krzk+dt, conor+dt, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-clk, WeiHao Li
We need a clock id to assign clock parent when use i2s 8ch as audio
device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
frequency we want.
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
include/dt-bindings/clock/rk3368-cru.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
index b951e29069..795e721957 100644
--- a/include/dt-bindings/clock/rk3368-cru.h
+++ b/include/dt-bindings/clock/rk3368-cru.h
@@ -183,6 +183,9 @@
#define HCLK_BUS 477
#define HCLK_PERI 478
+#define CLK_I2S_8CH_PRE 500
+#define CLK_I2S_8CH_FRAC 501
+
/* soft-reset indices */
#define SRST_CORE_B0 0
#define SRST_CORE_B1 1
--
2.39.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-05 13:23 ` [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC WeiHao Li
@ 2025-09-05 14:13 ` Krzysztof Kozlowski
2025-09-06 1:34 ` 李维豪
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-05 14:13 UTC (permalink / raw)
To: WeiHao Li, heiko, robh
Cc: krzk+dt, conor+dt, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-clk
On 05/09/2025 15:23, WeiHao Li wrote:
> We need a clock id to assign clock parent when use i2s 8ch as audio
> device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
> frequency we want.
>
> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> ---
> include/dt-bindings/clock/rk3368-cru.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> index b951e29069..795e721957 100644
> --- a/include/dt-bindings/clock/rk3368-cru.h
> +++ b/include/dt-bindings/clock/rk3368-cru.h
> @@ -183,6 +183,9 @@
> #define HCLK_BUS 477
> #define HCLK_PERI 478
>
> +#define CLK_I2S_8CH_PRE 500
479
> +#define CLK_I2S_8CH_FRAC 501
480, no?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-05 14:13 ` Krzysztof Kozlowski
@ 2025-09-06 1:34 ` 李维豪
2025-09-06 7:21 ` Krzysztof Kozlowski
0 siblings, 1 reply; 10+ messages in thread
From: 李维豪 @ 2025-09-06 1:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: heiko, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-clk
Hi,
Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月5日周五 22:13写道:
>
> On 05/09/2025 15:23, WeiHao Li wrote:
> > We need a clock id to assign clock parent when use i2s 8ch as audio
> > device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
> > frequency we want.
> >
> > Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> > ---
> > include/dt-bindings/clock/rk3368-cru.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> > index b951e29069..795e721957 100644
> > --- a/include/dt-bindings/clock/rk3368-cru.h
> > +++ b/include/dt-bindings/clock/rk3368-cru.h
> > @@ -183,6 +183,9 @@
> > #define HCLK_BUS 477
> > #define HCLK_PERI 478
> >
> > +#define CLK_I2S_8CH_PRE 500
>
> 479
>
> > +#define CLK_I2S_8CH_FRAC 501
>
> 480, no?
>
Neither of these clocks belong to the previous grouping in terms of
type, so I chose to start with a new integer id here.
Yours,
WeiHao
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-06 1:34 ` 李维豪
@ 2025-09-06 7:21 ` Krzysztof Kozlowski
2025-09-06 13:34 ` 李维豪
0 siblings, 1 reply; 10+ messages in thread
From: Krzysztof Kozlowski @ 2025-09-06 7:21 UTC (permalink / raw)
To: 李维豪
Cc: heiko, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-clk
On 06/09/2025 03:34, 李维豪 wrote:
> Hi,
>
> Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月5日周五 22:13写道:
>>
>> On 05/09/2025 15:23, WeiHao Li wrote:
>>> We need a clock id to assign clock parent when use i2s 8ch as audio
>>> device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
>>> frequency we want.
>>>
>>> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
>>> ---
>>> include/dt-bindings/clock/rk3368-cru.h | 3 +++
>>> 1 file changed, 3 insertions(+)
>>>
>>> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
>>> index b951e29069..795e721957 100644
>>> --- a/include/dt-bindings/clock/rk3368-cru.h
>>> +++ b/include/dt-bindings/clock/rk3368-cru.h
>>> @@ -183,6 +183,9 @@
>>> #define HCLK_BUS 477
>>> #define HCLK_PERI 478
>>>
>>> +#define CLK_I2S_8CH_PRE 500
>>
>> 479
>>
>>> +#define CLK_I2S_8CH_FRAC 501
>>
>> 480, no?
>>
>
> Neither of these clocks belong to the previous grouping in terms of
> type, so I chose to start with a new integer id here.
I don't know what is "previous grouping" here, but IDs are abstract and
are incremented by 1.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-06 7:21 ` Krzysztof Kozlowski
@ 2025-09-06 13:34 ` 李维豪
2025-09-06 13:57 ` Diederik de Haas
0 siblings, 1 reply; 10+ messages in thread
From: 李维豪 @ 2025-09-06 13:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: heiko, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-clk
Hi,
Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月6日周六 15:21写道:
>
> On 06/09/2025 03:34, 李维豪 wrote:
> > Hi,
> >
> > Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月5日周五 22:13写道:
> >>
> >> On 05/09/2025 15:23, WeiHao Li wrote:
> >>> We need a clock id to assign clock parent when use i2s 8ch as audio
> >>> device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
> >>> frequency we want.
> >>>
> >>> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
> >>> ---
> >>> include/dt-bindings/clock/rk3368-cru.h | 3 +++
> >>> 1 file changed, 3 insertions(+)
> >>>
> >>> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
> >>> index b951e29069..795e721957 100644
> >>> --- a/include/dt-bindings/clock/rk3368-cru.h
> >>> +++ b/include/dt-bindings/clock/rk3368-cru.h
> >>> @@ -183,6 +183,9 @@
> >>> #define HCLK_BUS 477
> >>> #define HCLK_PERI 478
> >>>
> >>> +#define CLK_I2S_8CH_PRE 500
> >>
> >> 479
> >>
> >>> +#define CLK_I2S_8CH_FRAC 501
> >>
> >> 480, no?
> >>
> >
> > Neither of these clocks belong to the previous grouping in terms of
> > type, so I chose to start with a new integer id here.
>
> I don't know what is "previous grouping" here, but IDs are abstract and
> are incremented by 1.
In the current kernel code, the RK3368 clock IDs are categorized by
SCLK, ACLK, PCLK, and HCLK.
However, for the I2S 8CH peripheral, the default MCLK output frequency
depends on I2S_8CH_PRE, which has four possible clock sources:
i2s_8ch_src, i2s_8ch_frac, ext_i2s, and xin12m.
The parent clock of i2s_8ch_frac is i2s_8ch_src, and the frequency of
i2s_8ch_src comes from either the CPLL or GPLL.
Due to the clock topology, CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC cannot
be simply categorized as SCLK, ACLK, PCLK, and HCLK mentioned above,
so I choose to start counting from a new ID.
If this way of assigning IDs is not appropriate, I can modify it to
increment based on the previous one.
Besh wishes,
WeiHao
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-06 13:34 ` 李维豪
@ 2025-09-06 13:57 ` Diederik de Haas
0 siblings, 0 replies; 10+ messages in thread
From: Diederik de Haas @ 2025-09-06 13:57 UTC (permalink / raw)
To: 李维豪, Krzysztof Kozlowski
Cc: heiko, robh, krzk+dt, conor+dt, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-clk
[-- Attachment #1: Type: text/plain, Size: 2223 bytes --]
On Sat Sep 6, 2025 at 3:34 PM CEST, 李维豪 wrote:
> Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月6日周六 15:21写道:
>> On 06/09/2025 03:34, 李维豪 wrote:
>> > Krzysztof Kozlowski <krzk@kernel.org> 于2025年9月5日周五 22:13写道:
>> >> On 05/09/2025 15:23, WeiHao Li wrote:
>> >>> We need a clock id to assign clock parent when use i2s 8ch as audio
>> >>> device, CLK_I2S_8CH_FRAC should be CLK_I2S_8CH_PRE parent so we can get
>> >>> frequency we want.
>> >>>
>> >>> Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
>> >>> ---
>> >>> include/dt-bindings/clock/rk3368-cru.h | 3 +++
>> >>> 1 file changed, 3 insertions(+)
>> >>>
>> >>> diff --git a/include/dt-bindings/clock/rk3368-cru.h b/include/dt-bindings/clock/rk3368-cru.h
>> >>> index b951e29069..795e721957 100644
>> >>> --- a/include/dt-bindings/clock/rk3368-cru.h
>> >>> +++ b/include/dt-bindings/clock/rk3368-cru.h
>> >>> @@ -183,6 +183,9 @@
>> >>> #define HCLK_BUS 477
>> >>> #define HCLK_PERI 478
>> >>>
>> >>> +#define CLK_I2S_8CH_PRE 500
>> >>
>> >> 479
>> >>
>> >>> +#define CLK_I2S_8CH_FRAC 501
>> >>
>> >> 480, no?
>> >>
>> >
>> > Neither of these clocks belong to the previous grouping in terms of
>> > type, so I chose to start with a new integer id here.
>>
>> I don't know what is "previous grouping" here, but IDs are abstract and
>> are incremented by 1.
>
> In the current kernel code, the RK3368 clock IDs are categorized by
> SCLK, ACLK, PCLK, and HCLK.
Maybe this helps understanding the discrepancy:
Starting with the rk3588 series, clock IDs are in the 'clock' binding
dir and named "rockchip,rk<SoC-id>-cru.h" and are numbered sequentially
with no gaps. And the reset IDs are in the 'reset' binding dir with the
same filename pattern.
With older SoC series, including rk3568*, both the clock and reset IDs
are in "clock/rk<SoC-id>-cru.h" where they are NOT sequentially
numbered and thus jumps in the numbering is not out of place there.
HTH,
Diederik
*) I have a local commit which moves the reset IDs to
"reset/rockchip,rk3568-cru.h", but I don't know how to do/fix the
numbering, so I never submitted it.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1 3/4] clk: rockchip: rk3368: use clock ids CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
2025-09-05 13:23 [PATCH v1 0/4] clk/rockchip: Fix I2S 8CH mclk output for RK3368 WeiHao Li
2025-09-05 13:23 ` [PATCH v1 1/4] clk: rockchip: rk3368: fix SCLK_I2S_8CH_OUT flags WeiHao Li
2025-09-05 13:23 ` [PATCH v1 2/4] dt-bindings: clock: rk3368: add CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC WeiHao Li
@ 2025-09-05 13:23 ` WeiHao Li
2025-09-05 13:23 ` [PATCH v1 4/4] arm64: dts: rockchip: Assign I2S 8 channel clock for rk3368 WeiHao Li
3 siblings, 0 replies; 10+ messages in thread
From: WeiHao Li @ 2025-09-05 13:23 UTC (permalink / raw)
To: heiko, robh
Cc: krzk+dt, conor+dt, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-clk, WeiHao Li
Export the clocks via the newly added clock-ids.
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
drivers/clk/rockchip/clk-rk3368.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 8159f643dc..1fb18c9596 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -244,7 +244,7 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
};
static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
- MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
+ MUX(CLK_I2S_8CH_PRE, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
@@ -367,7 +367,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(6), 1, GFLAGS),
- COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(CLK_I2S_8CH_FRAC, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
&rk3368_i2s_8ch_fracmux),
--
2.39.5
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 4/4] arm64: dts: rockchip: Assign I2S 8 channel clock for rk3368
2025-09-05 13:23 [PATCH v1 0/4] clk/rockchip: Fix I2S 8CH mclk output for RK3368 WeiHao Li
` (2 preceding siblings ...)
2025-09-05 13:23 ` [PATCH v1 3/4] clk: rockchip: rk3368: use clock ids " WeiHao Li
@ 2025-09-05 13:23 ` WeiHao Li
3 siblings, 0 replies; 10+ messages in thread
From: WeiHao Li @ 2025-09-05 13:23 UTC (permalink / raw)
To: heiko, robh
Cc: krzk+dt, conor+dt, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, linux-clk, WeiHao Li
I2S 8CH needs assign correct clock to output frequency wanted. This
patch assign CLK_I2S_8CH_FRAC as CLK_I2S_8CH_PRE parents.
Signed-off-by: WeiHao Li <cn.liweihao@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk3368.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3368.dtsi b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
index cdcbc0a944..d931b5f5ac 100644
--- a/arch/arm64/boot/dts/rockchip/rk3368.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3368.dtsi
@@ -862,6 +862,8 @@ i2s_8ch: i2s-8ch@ff898000 {
compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xff898000 0x0 0x1000>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_I2S_8CH_PRE>;
+ assigned-clock-parents = <&cru CLK_I2S_8CH_FRAC>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
dmas = <&dmac_bus 0>, <&dmac_bus 1>;
--
2.39.5
^ permalink raw reply related [flat|nested] 10+ messages in thread