From: Jason Gunthorpe <jgg@nvidia.com>
To: Nicolin Chen <nicolinc@nvidia.com>
Cc: will@kernel.org, robin.murphy@arm.com, joro@8bytes.org,
jean-philippe@linaro.org, miko.lenczewski@arm.com,
balbirs@nvidia.com, peterz@infradead.org, smostafa@google.com,
kevin.tian@intel.com, praan@google.com, zhangzekun11@huawei.com,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, patches@lists.linux.dev
Subject: Re: [PATCH rfcv1 7/8] iommu/arm-smmu-v3: Add arm_smmu_invs based arm_smmu_domain_inv_range()
Date: Mon, 8 Sep 2025 15:24:04 -0300 [thread overview]
Message-ID: <20250908182404.GH789684@nvidia.com> (raw)
In-Reply-To: <aL8ePHvQ25LUU81J@nvidia.com>
On Mon, Sep 08, 2025 at 11:19:40AM -0700, Nicolin Chen wrote:
> On Mon, Sep 08, 2025 at 12:39:11PM -0300, Jason Gunthorpe wrote:
> > On Sat, Sep 06, 2025 at 01:12:33AM -0700, Nicolin Chen wrote:
> >
> > > I know that performance-wise, this piece will be a quick respin,
> > > as the attach side releases the lock very fast. It still looks
> > > a bit complicated. And practically, it would respin even if the
> > > attachment removes a non-PCI device, right?
> >
> > If you are paying the cost of taking the lock then it should become
> > fully locked and consistent.
>
> Well, the point is that the reader doesn't know if an ATS entry
> is getting removed, and it can only speculate by looking at the
> full list.
It doesn't care. It knows if it has to get a full lock or not, that's
it.
> So, would it be better to just always take the read lock, while
> applying the ATS condition to the writer side:
No, the whole optimization is to avoid read side locking on the fairly
common no-ATS case.
Always taking the lock destroys that.
Jsaon
next prev parent reply other threads:[~2025-09-09 2:28 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-14 1:25 [PATCH rfcv1 0/8] iommu/arm-smmu-v3: Introduce an RCU-protected invalidation array Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 1/8] iommu/arm-smmu-v3: Clear cmds->num after arm_smmu_cmdq_batch_submit Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 2/8] iommu/arm-smmu-v3: Explicitly set smmu_domain->stage for SVA Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 3/8] iommu/arm-smmu-v3: Add an inline arm_smmu_domain_free() Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 4/8] iommu/arm-smmu-v3: Introduce a per-domain arm_smmu_invs array Nicolin Chen
2025-08-26 19:50 ` Jason Gunthorpe
2025-08-27 0:49 ` Nicolin Chen
2025-08-27 16:48 ` Jason Gunthorpe
2025-08-27 17:19 ` Nicolin Chen
2025-08-28 12:37 ` Jason Gunthorpe
2025-08-27 20:00 ` Jason Gunthorpe
2025-09-06 8:16 ` Nicolin Chen
2025-09-08 15:51 ` Jason Gunthorpe
2025-09-08 18:20 ` Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 5/8] iommu/arm-smmu-v3: Pre-allocate a per-master invalidation array Nicolin Chen
2025-08-26 19:56 ` Jason Gunthorpe
2025-09-06 7:45 ` Nicolin Chen
2025-09-08 15:36 ` Jason Gunthorpe
2025-08-14 1:25 ` [PATCH rfcv1 6/8] iommu/arm-smmu-v3: Populate smmu_domain->invs when attaching masters Nicolin Chen
2025-08-27 18:21 ` Jason Gunthorpe
2025-09-06 7:52 ` Nicolin Chen
2025-09-06 8:20 ` Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 7/8] iommu/arm-smmu-v3: Add arm_smmu_invs based arm_smmu_domain_inv_range() Nicolin Chen
2025-08-27 18:49 ` Jason Gunthorpe
2025-09-06 8:12 ` Nicolin Chen
2025-09-08 15:39 ` Jason Gunthorpe
2025-09-08 18:19 ` Nicolin Chen
2025-09-08 18:24 ` Jason Gunthorpe [this message]
2025-09-08 18:45 ` Nicolin Chen
2025-08-14 1:25 ` [PATCH rfcv1 8/8] iommu/arm-smmu-v3: Perform per-domain invalidations using arm_smmu_invs Nicolin Chen
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