[PATCH v1 1/2] ARM: dts: samsung: Add cache information to the Exynos4412 SoCS

[PATCH v1 1/2] ARM: dts: samsung: Add cache information to the Exynos4412 SoCS

[Anand Moon]

As per the Exynos 4412 user manaual add missing cache information to
the Exynos 4412 SoC.

- Each Cortex-A9 core has 32KB of L1 instruction cache available and
	32KB of L1 data cache available.
- Along with 1M unified L2 cache.

Features of ARM Cortex-A9
- Optimized L1 caches for system performance and power.
- Integrated 1 MB L2 Cache using standard compiled RAMs.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 arch/arm/boot/dts/samsung/exynos4412.dtsi | 37 +++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/arch/arm/boot/dts/samsung/exynos4412.dtsi b/arch/arm/boot/dts/samsung/exynos4412.dtsi
index dcbe0ce6180f..d133c8a8e8d4 100644
--- a/arch/arm/boot/dts/samsung/exynos4412.dtsi
+++ b/arch/arm/boot/dts/samsung/exynos4412.dtsi
@@ -48,6 +48,13 @@ cpu0: cpu@a00 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu@a01 {
@@ -58,6 +65,13 @@ cpu1: cpu@a01 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu@a02 {
@@ -68,6 +82,13 @@ cpu2: cpu@a02 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu@a03 {
@@ -78,6 +99,22 @@ cpu3: cpu@a03 {
 			clock-names = "cpu";
 			operating-points-v2 = <&cpu0_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x100000>; /* L2, 1M */
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};
 

base-commit: dc1c8034e31b14a2e5e212104ec508aec44ce1b9
-- 
2.44.0

[PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Anand Moon]

As per Exynos 5422 user manual add missing cache information to
the Exynos542x SoC.

- Each Cortex-A7 core has 32 KB of instruction cache and
	32 KB of L1 data cache available.
- Each Cortex-A15 core has 32 KB of L1 instruction cache and
	32 KB of L1 data cache available.
- The little (A7) cluster has 512 KB of unified L2 cache available.
- The big (A15) cluster has 2 MB of unified L2 cache available.

Features:
- Exynos 5422 support cache coherency interconnect (CCI) bus with
  L2 cache snooping capability. This hardware automatic L2 cache
  snooping removes the efforts of synchronizing the contents of the
  two L2 caches in core switching event.

Signed-off-by: Anand Moon <linux.amoon@gmail.com>
---
 .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
index 412a0bb4b988..9b9b2bdfb522 100644
--- a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
@@ -59,6 +59,13 @@ cpu0: cpu@100 {
 			reg = <0x100>;
 			clocks = <&clock CLK_KFC_CLK>;
 			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -72,6 +79,13 @@ cpu1: cpu@101 {
 			reg = <0x101>;
 			clocks = <&clock CLK_KFC_CLK>;
 			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -85,6 +99,13 @@ cpu2: cpu@102 {
 			reg = <0x102>;
 			clocks = <&clock CLK_KFC_CLK>;
 			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -98,6 +119,13 @@ cpu3: cpu@103 {
 			reg = <0x103>;
 			clocks = <&clock CLK_KFC_CLK>;
 			clock-frequency = <1000000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a7>;
 			cci-control-port = <&cci_control0>;
 			operating-points-v2 = <&cluster_a7_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -111,6 +139,13 @@ cpu4: cpu@0 {
 			reg = <0x0>;
 			clocks = <&clock CLK_ARM_CLK>;
 			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -124,6 +159,13 @@ cpu5: cpu@1 {
 			reg = <0x1>;
 			clocks = <&clock CLK_ARM_CLK>;
 			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -137,6 +179,13 @@ cpu6: cpu@2 {
 			reg = <0x2>;
 			clocks = <&clock CLK_ARM_CLK>;
 			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -150,12 +199,37 @@ cpu7: cpu@3 {
 			reg = <0x3>;
 			clocks = <&clock CLK_ARM_CLK>;
 			clock-frequency = <1800000000>;
+			d-cache-line-size = <32>;
+			d-cache-size = <0x8000>;
+			d-cache-sets = <32>;
+			i-cache-line-size = <32>;
+			i-cache-size = <0x8000>;
+			i-cache-sets = <32>;
+			next-level-cache = <&L2_a15>;
 			cci-control-port = <&cci_control1>;
 			operating-points-v2 = <&cluster_a15_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
 			capacity-dmips-mhz = <1024>;
 			dynamic-power-coefficient = <310>;
 		};
+
+		L2_a7: l2-cache-cluster0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x80000>;	/* L2. 512 KB */
+			cache-line-size = <64>;
+			cache-sets = <512>;
+		};
+
+		L2_a15: l2-cache-cluster1 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x200000>; /* L2, 2M */
+			cache-line-size = <64>;
+			cache-sets = <512>;
+		};
 	};
 };
 
-- 
2.44.0

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Marek Szyprowski]

On 30.07.2024 11:13, Anand Moon wrote:
> As per Exynos 5422 user manual add missing cache information to
> the Exynos542x SoC.
>
> - Each Cortex-A7 core has 32 KB of instruction cache and
> 	32 KB of L1 data cache available.
> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> 	32 KB of L1 data cache available.
> - The little (A7) cluster has 512 KB of unified L2 cache available.
> - The big (A15) cluster has 2 MB of unified L2 cache available.
>
> Features:
> - Exynos 5422 support cache coherency interconnect (CCI) bus with
>    L2 cache snooping capability. This hardware automatic L2 cache
>    snooping removes the efforts of synchronizing the contents of the
>    two L2 caches in core switching event.
>
> Signed-off-by: Anand Moon <linux.amoon@gmail.com>


The provided values are not correct. Please refer to commit 5f41f9198f29 
("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU 
cores"), which adds workaround for different l1 icache line size between 
big and little CPUs. This workaround gets enabled on all Exynos542x/5800 
boards.


> ---
>   .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++
>   1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> index 412a0bb4b988..9b9b2bdfb522 100644
> --- a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> @@ -59,6 +59,13 @@ cpu0: cpu@100 {
>   			reg = <0x100>;
>   			clocks = <&clock CLK_KFC_CLK>;
>   			clock-frequency = <1000000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a7>;
>   			cci-control-port = <&cci_control0>;
>   			operating-points-v2 = <&cluster_a7_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -72,6 +79,13 @@ cpu1: cpu@101 {
>   			reg = <0x101>;
>   			clocks = <&clock CLK_KFC_CLK>;
>   			clock-frequency = <1000000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a7>;
>   			cci-control-port = <&cci_control0>;
>   			operating-points-v2 = <&cluster_a7_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -85,6 +99,13 @@ cpu2: cpu@102 {
>   			reg = <0x102>;
>   			clocks = <&clock CLK_KFC_CLK>;
>   			clock-frequency = <1000000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a7>;
>   			cci-control-port = <&cci_control0>;
>   			operating-points-v2 = <&cluster_a7_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -98,6 +119,13 @@ cpu3: cpu@103 {
>   			reg = <0x103>;
>   			clocks = <&clock CLK_KFC_CLK>;
>   			clock-frequency = <1000000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a7>;
>   			cci-control-port = <&cci_control0>;
>   			operating-points-v2 = <&cluster_a7_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -111,6 +139,13 @@ cpu4: cpu@0 {
>   			reg = <0x0>;
>   			clocks = <&clock CLK_ARM_CLK>;
>   			clock-frequency = <1800000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a15>;
>   			cci-control-port = <&cci_control1>;
>   			operating-points-v2 = <&cluster_a15_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -124,6 +159,13 @@ cpu5: cpu@1 {
>   			reg = <0x1>;
>   			clocks = <&clock CLK_ARM_CLK>;
>   			clock-frequency = <1800000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a15>;
>   			cci-control-port = <&cci_control1>;
>   			operating-points-v2 = <&cluster_a15_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -137,6 +179,13 @@ cpu6: cpu@2 {
>   			reg = <0x2>;
>   			clocks = <&clock CLK_ARM_CLK>;
>   			clock-frequency = <1800000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a15>;
>   			cci-control-port = <&cci_control1>;
>   			operating-points-v2 = <&cluster_a15_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
> @@ -150,12 +199,37 @@ cpu7: cpu@3 {
>   			reg = <0x3>;
>   			clocks = <&clock CLK_ARM_CLK>;
>   			clock-frequency = <1800000000>;
> +			d-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;
> +			d-cache-sets = <32>;
> +			i-cache-line-size = <32>;
> +			i-cache-size = <0x8000>;
> +			i-cache-sets = <32>;
> +			next-level-cache = <&L2_a15>;
>   			cci-control-port = <&cci_control1>;
>   			operating-points-v2 = <&cluster_a15_opp_table>;
>   			#cooling-cells = <2>; /* min followed by max */
>   			capacity-dmips-mhz = <1024>;
>   			dynamic-power-coefficient = <310>;
>   		};
> +
> +		L2_a7: l2-cache-cluster0 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x80000>;	/* L2. 512 KB */
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +		};
> +
> +		L2_a15: l2-cache-cluster1 {
> +			compatible = "cache";
> +			cache-level = <2>;
> +			cache-unified;
> +			cache-size = <0x200000>; /* L2, 2M */
> +			cache-line-size = <64>;
> +			cache-sets = <512>;
> +		};
>   	};
>   };
>   

Best regards
-- 
Marek Szyprowski, PhD
Samsung R&D Institute Poland

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Anand Moon]

Hi Marek,

On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>
>
> On 30.07.2024 11:13, Anand Moon wrote:
> > As per Exynos 5422 user manual add missing cache information to
> > the Exynos542x SoC.
> >
> > - Each Cortex-A7 core has 32 KB of instruction cache and
> >       32 KB of L1 data cache available.
> > - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> >       32 KB of L1 data cache available.
> > - The little (A7) cluster has 512 KB of unified L2 cache available.
> > - The big (A15) cluster has 2 MB of unified L2 cache available.
> >
> > Features:
> > - Exynos 5422 support cache coherency interconnect (CCI) bus with
> >    L2 cache snooping capability. This hardware automatic L2 cache
> >    snooping removes the efforts of synchronizing the contents of the
> >    two L2 caches in core switching event.
> >
> > Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>
>
> The provided values are not correct. Please refer to commit 5f41f9198f29
> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
> cores"), which adds workaround for different l1 icache line size between
> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
> boards.
>
Ok, I have just referred to the Exynos 5422 user manual for this patch,
This patch is just updating the cache size for CPU for big.litle architecture..

Thanks
-Anand
>
> > ---
> >   .../arm/boot/dts/samsung/exynos5422-cpus.dtsi | 74 +++++++++++++++++++
> >   1 file changed, 74 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> > index 412a0bb4b988..9b9b2bdfb522 100644
> > --- a/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> > +++ b/arch/arm/boot/dts/samsung/exynos5422-cpus.dtsi
> > @@ -59,6 +59,13 @@ cpu0: cpu@100 {
> >                       reg = <0x100>;
> >                       clocks = <&clock CLK_KFC_CLK>;
> >                       clock-frequency = <1000000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a7>;
> >                       cci-control-port = <&cci_control0>;
> >                       operating-points-v2 = <&cluster_a7_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -72,6 +79,13 @@ cpu1: cpu@101 {
> >                       reg = <0x101>;
> >                       clocks = <&clock CLK_KFC_CLK>;
> >                       clock-frequency = <1000000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a7>;
> >                       cci-control-port = <&cci_control0>;
> >                       operating-points-v2 = <&cluster_a7_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -85,6 +99,13 @@ cpu2: cpu@102 {
> >                       reg = <0x102>;
> >                       clocks = <&clock CLK_KFC_CLK>;
> >                       clock-frequency = <1000000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a7>;
> >                       cci-control-port = <&cci_control0>;
> >                       operating-points-v2 = <&cluster_a7_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -98,6 +119,13 @@ cpu3: cpu@103 {
> >                       reg = <0x103>;
> >                       clocks = <&clock CLK_KFC_CLK>;
> >                       clock-frequency = <1000000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a7>;
> >                       cci-control-port = <&cci_control0>;
> >                       operating-points-v2 = <&cluster_a7_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -111,6 +139,13 @@ cpu4: cpu@0 {
> >                       reg = <0x0>;
> >                       clocks = <&clock CLK_ARM_CLK>;
> >                       clock-frequency = <1800000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a15>;
> >                       cci-control-port = <&cci_control1>;
> >                       operating-points-v2 = <&cluster_a15_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -124,6 +159,13 @@ cpu5: cpu@1 {
> >                       reg = <0x1>;
> >                       clocks = <&clock CLK_ARM_CLK>;
> >                       clock-frequency = <1800000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a15>;
> >                       cci-control-port = <&cci_control1>;
> >                       operating-points-v2 = <&cluster_a15_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -137,6 +179,13 @@ cpu6: cpu@2 {
> >                       reg = <0x2>;
> >                       clocks = <&clock CLK_ARM_CLK>;
> >                       clock-frequency = <1800000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a15>;
> >                       cci-control-port = <&cci_control1>;
> >                       operating-points-v2 = <&cluster_a15_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> > @@ -150,12 +199,37 @@ cpu7: cpu@3 {
> >                       reg = <0x3>;
> >                       clocks = <&clock CLK_ARM_CLK>;
> >                       clock-frequency = <1800000000>;
> > +                     d-cache-line-size = <32>;
> > +                     d-cache-size = <0x8000>;
> > +                     d-cache-sets = <32>;
> > +                     i-cache-line-size = <32>;
> > +                     i-cache-size = <0x8000>;
> > +                     i-cache-sets = <32>;
> > +                     next-level-cache = <&L2_a15>;
> >                       cci-control-port = <&cci_control1>;
> >                       operating-points-v2 = <&cluster_a15_opp_table>;
> >                       #cooling-cells = <2>; /* min followed by max */
> >                       capacity-dmips-mhz = <1024>;
> >                       dynamic-power-coefficient = <310>;
> >               };
> > +
> > +             L2_a7: l2-cache-cluster0 {
> > +                     compatible = "cache";
> > +                     cache-level = <2>;
> > +                     cache-unified;
> > +                     cache-size = <0x80000>; /* L2. 512 KB */
> > +                     cache-line-size = <64>;
> > +                     cache-sets = <512>;
> > +             };
> > +
> > +             L2_a15: l2-cache-cluster1 {
> > +                     compatible = "cache";
> > +                     cache-level = <2>;
> > +                     cache-unified;
> > +                     cache-size = <0x200000>; /* L2, 2M */
> > +                     cache-line-size = <64>;
> > +                     cache-sets = <512>;
> > +             };
> >       };
> >   };
> >
>
> Best regards
> --
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
>

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Krzysztof Kozlowski]

On 30/07/2024 14:06, Anand Moon wrote:
> Hi Marek,
> 
> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>
>>
>> On 30.07.2024 11:13, Anand Moon wrote:
>>> As per Exynos 5422 user manual add missing cache information to
>>> the Exynos542x SoC.
>>>
>>> - Each Cortex-A7 core has 32 KB of instruction cache and
>>>       32 KB of L1 data cache available.
>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
>>>       32 KB of L1 data cache available.
>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
>>>
>>> Features:
>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
>>>    L2 cache snooping capability. This hardware automatic L2 cache
>>>    snooping removes the efforts of synchronizing the contents of the
>>>    two L2 caches in core switching event.
>>>
>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>
>>
>> The provided values are not correct. Please refer to commit 5f41f9198f29
>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
>> cores"), which adds workaround for different l1 icache line size between
>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
>> boards.
>>
> Ok, I have just referred to the Exynos 5422 user manual for this patch,
> This patch is just updating the cache size for CPU for big.litle architecture..
> 

Let me get it right. Marek's comment was that you used wrong values.
Marek also provided rationale for this. Now your reply is that you
update cache size? Sorry, I fail how you address Marek's comment.

Do not repeat what the patch is doing. We all can see it. Instead
respond to the comment with some sort of arguments.

Best regards,
Krzysztof

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Anand Moon]

Hi Krzysztof,

On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 30/07/2024 14:06, Anand Moon wrote:
> > Hi Marek,
> >
> > On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >>
> >>
> >> On 30.07.2024 11:13, Anand Moon wrote:
> >>> As per Exynos 5422 user manual add missing cache information to
> >>> the Exynos542x SoC.
> >>>
> >>> - Each Cortex-A7 core has 32 KB of instruction cache and
> >>>       32 KB of L1 data cache available.
> >>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> >>>       32 KB of L1 data cache available.
> >>> - The little (A7) cluster has 512 KB of unified L2 cache available.
> >>> - The big (A15) cluster has 2 MB of unified L2 cache available.
> >>>
> >>> Features:
> >>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
> >>>    L2 cache snooping capability. This hardware automatic L2 cache
> >>>    snooping removes the efforts of synchronizing the contents of the
> >>>    two L2 caches in core switching event.
> >>>
> >>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>
> >>
> >> The provided values are not correct. Please refer to commit 5f41f9198f29
> >> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
> >> cores"), which adds workaround for different l1 icache line size between
> >> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
> >> boards.
> >>
> > Ok, I have just referred to the Exynos 5422 user manual for this patch,
> > This patch is just updating the cache size for CPU for big.litle architecture..
> >
>
> Let me get it right. Marek's comment was that you used wrong values.
> Marek also provided rationale for this. Now your reply is that you
> update cache size? Sorry, I fail how you address Marek's comment.
>
> Do not repeat what the patch is doing. We all can see it. Instead
> respond to the comment with some sort of arguments.
>

Ok, If I am not wrong  icache_size is hard-coded in the above commit.

+#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
+.globl icache_size
+       .data
+       .align  2
+icache_size:
+       .long   64
+       .text
+#endif

In the check_cpu_icache_size function, we read the control reg
and recalculate the icache_size.
if there mismatch we re-apply the Icache_size,

So dts passed values do not apply over here,

> Best regards,
> Krzysztof
>

Thanks
-Anand

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Krzysztof Kozlowski]

On 30/07/2024 15:20, Anand Moon wrote:
> Hi Krzysztof,
> 
> On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>
>> On 30/07/2024 14:06, Anand Moon wrote:
>>> Hi Marek,
>>>
>>> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>>>
>>>>
>>>> On 30.07.2024 11:13, Anand Moon wrote:
>>>>> As per Exynos 5422 user manual add missing cache information to
>>>>> the Exynos542x SoC.
>>>>>
>>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
>>>>>       32 KB of L1 data cache available.
>>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
>>>>>       32 KB of L1 data cache available.
>>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
>>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
>>>>>
>>>>> Features:
>>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
>>>>>    L2 cache snooping capability. This hardware automatic L2 cache
>>>>>    snooping removes the efforts of synchronizing the contents of the
>>>>>    two L2 caches in core switching event.
>>>>>
>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>>>
>>>>
>>>> The provided values are not correct. Please refer to commit 5f41f9198f29
>>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
>>>> cores"), which adds workaround for different l1 icache line size between
>>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
>>>> boards.
>>>>
>>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
>>> This patch is just updating the cache size for CPU for big.litle architecture..
>>>
>>
>> Let me get it right. Marek's comment was that you used wrong values.
>> Marek also provided rationale for this. Now your reply is that you
>> update cache size? Sorry, I fail how you address Marek's comment.
>>
>> Do not repeat what the patch is doing. We all can see it. Instead
>> respond to the comment with some sort of arguments.
>>
> 
> Ok, If I am not wrong  icache_size is hard-coded in the above commit.
> 
> +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
> +.globl icache_size
> +       .data
> +       .align  2
> +icache_size:
> +       .long   64
> +       .text
> +#endif
> 
> In the check_cpu_icache_size function, we read the control reg
> and recalculate the icache_size.
> if there mismatch we re-apply the Icache_size,
> 
> So dts passed values do not apply over here,

So you provide incorrect values in terms of them being ignored? Then do
not provide at all.

Best regards,
Krzysztof

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Anand Moon]

Hi Krzysztof,

On Tue, 30 Jul 2024 at 18:53, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 30/07/2024 15:20, Anand Moon wrote:
> > Hi Krzysztof,
> >
> > On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>
> >> On 30/07/2024 14:06, Anand Moon wrote:
> >>> Hi Marek,
> >>>
> >>> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >>>>
> >>>>
> >>>> On 30.07.2024 11:13, Anand Moon wrote:
> >>>>> As per the Exynos 5422 user manual add missing cache information to
> >>>>> the Exynos542x SoC.
> >>>>>
> >>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
> >>>>>       32 KB of L1 data cache available.
> >>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> >>>>>       32 KB of L1 data cache available.
> >>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
> >>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
> >>>>>
> >>>>> Features:
> >>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
> >>>>>    L2 cache snooping capability. This hardware automatic L2 cache
> >>>>>    snooping removes the efforts of synchronizing the contents of the
> >>>>>    two L2 caches in core switching event.
> >>>>>
> >>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>>>
> >>>>
> >>>> The provided values are not correct. Please refer to commit 5f41f9198f29
> >>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
> >>>> cores"), which adds workaround for different l1 icache line size between
> >>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
> >>>> boards.
> >>>>
> >>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
> >>> This patch is just updating the cache size for CPU for big.litle architecture..
> >>>
> >>
> >> Let me get it right. Marek's comment was that you used wrong values.
> >> Marek also provided rationale for this. Now your reply is that you
> >> update cache size? Sorry, I fail how you address Marek's comment.
> >>
> >> Do not repeat what the patch is doing. We all can see it. Instead
> >> respond to the comment with some sort of arguments.
> >>
> >
> > Ok, If I am not wrong  icache_size is hard-coded in the above commit.
> >
> > +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
> > +.globl icache_size
> > +       .data
> > +       .align  2
> > +icache_size:
> > +       .long   64
> > +       .text
> > +#endif
> >
> > In the check_cpu_icache_size function, we read the control reg
> > and recalculate the icache_size.
> > if there mismatch we re-apply the Icache_size,
> >
> > So dts passed values do not apply over here,
>
> So you provide incorrect values in terms of them being ignored? Then do
> not provide at all.
>
I will drop the icache and dcache values and just pass the L2_a7 and
L2_a15, value
Is this ok for you?

Earlier, I have tried to verify this information in /sys and /proc
to verify the changes as ARM does not populate this information.

> Best regards,
> Krzysztof
>
Thanks
-Anand

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Anand Moon]

Hi Krzysztof, Marek,

On Tue, 30 Jul 2024 at 20:32, Anand Moon <linux.amoon@gmail.com> wrote:
>
> Hi Krzysztof,
>
> On Tue, 30 Jul 2024 at 18:53, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >
> > On 30/07/2024 15:20, Anand Moon wrote:
> > > Hi Krzysztof,
> > >
> > > On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> > >>
> > >> On 30/07/2024 14:06, Anand Moon wrote:
> > >>> Hi Marek,
> > >>>
> > >>> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> > >>>>
> > >>>>
> > >>>> On 30.07.2024 11:13, Anand Moon wrote:
> > >>>>> As per the Exynos 5422 user manual add missing cache information to
> > >>>>> the Exynos542x SoC.
> > >>>>>
> > >>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
> > >>>>>       32 KB of L1 data cache available.
> > >>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> > >>>>>       32 KB of L1 data cache available.
> > >>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
> > >>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
> > >>>>>
> > >>>>> Features:
> > >>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
> > >>>>>    L2 cache snooping capability. This hardware automatic L2 cache
> > >>>>>    snooping removes the efforts of synchronizing the contents of the
> > >>>>>    two L2 caches in core switching event.
> > >>>>>
> > >>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > >>>>
> > >>>>
> > >>>> The provided values are not correct. Please refer to commit 5f41f9198f29
> > >>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
> > >>>> cores"), which adds workaround for different l1 icache line size between
> > >>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
> > >>>> boards.
> > >>>>
> > >>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
> > >>> This patch is just updating the cache size for CPU for big.litle architecture..
> > >>>
> > >>
> > >> Let me get it right. Marek's comment was that you used wrong values.
> > >> Marek also provided rationale for this. Now your reply is that you
> > >> update cache size? Sorry, I fail how you address Marek's comment.
> > >>
> > >> Do not repeat what the patch is doing. We all can see it. Instead
> > >> respond to the comment with some sort of arguments.
> > >>
> > >
> > > Ok, If I am not wrong  icache_size is hard-coded in the above commit.
> > >
> > > +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
> > > +.globl icache_size
> > > +       .data
> > > +       .align  2
> > > +icache_size:
> > > +       .long   64
> > > +       .text
> > > +#endif
> > >
> > > In the check_cpu_icache_size function, we read the control reg
> > > and recalculate the icache_size.
> > > if there mismatch we re-apply the Icache_size,
> > >
> > > So dts passed values do not apply over here,
> >
> > So you provide incorrect values in terms of them being ignored? Then do
> > not provide at all.
> >
> I will drop the icache and dcache values and just pass the L2_a7 and
> L2_a15, value
> Is this ok for you?
>
> Earlier, I have tried to verify this information in /sys and /proc
> to verify the changes as ARM does not populate this information.
>
Here's an article that provides detailed insights into the cache feature.
[0] http://jake.dothome.co.kr/cache4/

The values associated with L1 and L2 caches indicate their respective sizes,
as specified in the ARM Technical Reference Manual (TRM) below.

Cortex-A15 L2 cache controller
[0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller

Cortex-A7 L2 cache controller
[1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller

These changes help define a fixed cache size, ensuring that active pages
are mapped correctly within the expected cache boundaries.

Here is the small test case using perf
Before

$ sudo perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact

Simulated Cache Miss Time (avg): 4766632 ns
Factorial(10) = 3628800

 Performance counter stats for './fact':

            926328      armv7_cortex_a15/L1-dcache-loads/
     <not counted>      armv7_cortex_a7/L1-dcache-loads/
                         (0.00%)
             16510      armv7_cortex_a15/L1-dcache-load-misses/ #
1.78% of all L1-dcache accesses
     <not counted>      armv7_cortex_a7/L1-dcache-load-misses/
                               (0.00%)

       0.008970031 seconds time elapsed

       0.000000000 seconds user
       0.009673000 seconds sys

After
$ sudo perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact
Simulated Cache Miss Time (avg): 4623272 ns
Factorial(10) = 3628800

 Performance counter stats for './fact':

            930570      armv7_cortex_a15/L1-dcache-loads/
     <not counted>      armv7_cortex_a7/L1-dcache-loads/
                         (0.00%)
              4755      armv7_cortex_a15/L1-dcache-load-misses/ #
0.51% of all L1-dcache accesses
     <not counted>      armv7_cortex_a7/L1-dcache-load-misses/
                               (0.00%)

       0.011068250 seconds time elapsed

       0.000000000 seconds user
       0.010793000 seconds sys

Thanks
-Anand

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Henrik Grimler]

Hi Anand,

Thanks for working on this!

On Tue, Sep 09, 2025 at 07:29:31PM +0530, Anand Moon wrote:
[ ... ]
> > > >>>> On 30.07.2024 11:13, Anand Moon wrote:
> > > >>>>> As per the Exynos 5422 user manual add missing cache information to
> > > >>>>> the Exynos542x SoC.
> > > >>>>>
> > > >>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
> > > >>>>>       32 KB of L1 data cache available.
> > > >>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> > > >>>>>       32 KB of L1 data cache available.
> > > >>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
> > > >>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
> > > >>>>>
> > > >>>>> Features:
> > > >>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
> > > >>>>>    L2 cache snooping capability. This hardware automatic L2 cache
> > > >>>>>    snooping removes the efforts of synchronizing the contents of the
> > > >>>>>    two L2 caches in core switching event.
> > > >>>>>
> > > >>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> > > >>>>
> > > >>>>
> > > >>>> The provided values are not correct. Please refer to commit 5f41f9198f29
> > > >>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
> > > >>>> cores"), which adds workaround for different l1 icache line size between
> > > >>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
> > > >>>> boards.
> > > >>>>
> > > >>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
> > > >>> This patch is just updating the cache size for CPU for big.litle architecture..

I do not have access to the 5422 manual unfortunately, but if I add
some prints in the code from the commit Marek referenced:

```diff
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -173,6 +173,7 @@ void check_cpu_icache_size(int cpuid)
        asm("mrc p15, 0, %0, c0, c0, 1" : "=r" (ctr));
 
        size = 1 << ((ctr & 0xf) + 2);
+       pr_warn("CPU%u: icache line size: %u, size %u\n", cpuid, icache_size, size);
        if (cpuid != 0 && icache_size != size)
                pr_info("CPU%u: detected I-Cache line size mismatch, workaround enabled\n",
                        cpuid);
```

Then we get in dmesg:

CPU0: icache line size: 64, size 32
CPU1: icache line size: 32, size 32
CPU2: icache line size: 32, size 32
CPU3: icache line size: 32, size 32
CPU4: icache line size: 32, size 64
CPU5: icache line size: 32, size 64
CPU6: icache line size: 32, size 64
CPU7: icache line size: 32, size 64

I interpret this as that the i-cache-line-size property of CPU4, 5, 6
and 7 (i.e. cpu@0, cpu@1, cpu@2 and cpu@4) should be 64 instead of 32.

Not sure about the other properties..

> Here's an article that provides detailed insights into the cache feature.
> [0] http://jake.dothome.co.kr/cache4/
> 
> The values associated with L1 and L2 caches indicate their respective sizes,
> as specified in the ARM Technical Reference Manual (TRM) below.
> 
> Cortex-A15 L2 cache controller
> [0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller
> 
> Cortex-A7 L2 cache controller
> [1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller
> 
> These changes help define a fixed cache size, ensuring that active pages
> are mapped correctly within the expected cache boundaries.
> 
> Here is the small test case using perf
> Before
> 
> $ sudo perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact
> 
> Simulated Cache Miss Time (avg): 4766632 ns
> Factorial(10) = 3628800
> 
>  Performance counter stats for './fact':
> 
>             926328      armv7_cortex_a15/L1-dcache-loads/
>      <not counted>      armv7_cortex_a7/L1-dcache-loads/
>                          (0.00%)
>              16510      armv7_cortex_a15/L1-dcache-load-misses/ #
> 1.78% of all L1-dcache accesses
>      <not counted>      armv7_cortex_a7/L1-dcache-load-misses/
>                                (0.00%)
> 
>        0.008970031 seconds time elapsed
> 
>        0.000000000 seconds user
>        0.009673000 seconds sys
> 
> After
> $ sudo perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact
> Simulated Cache Miss Time (avg): 4623272 ns
> Factorial(10) = 3628800
> 
>  Performance counter stats for './fact':
> 
>             930570      armv7_cortex_a15/L1-dcache-loads/
>      <not counted>      armv7_cortex_a7/L1-dcache-loads/
>                          (0.00%)
>               4755      armv7_cortex_a15/L1-dcache-load-misses/ #
> 0.51% of all L1-dcache accesses
>      <not counted>      armv7_cortex_a7/L1-dcache-load-misses/
>                                (0.00%)
> 
>        0.011068250 seconds time elapsed
> 
>        0.000000000 seconds user
>        0.010793000 seconds sys

I tried out the same test on my odroid-xu4, but was not able to
reliably get the same improvement. Cache misses varied between around
0.8 % to around 2.8 %. This was with a desktop UI installed and
though, will try it out in a headless installation in the next few
days, and perhaps try it on exynos5800 as well.

Might be worth also testing on both small and big cores, like:

$ sudo taskset -c 0,1,2,3 perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact
$ sudo taskset -c 4,5,6,7 perf stat -e L1-dcache-loads,L1-dcache-load-misses ./fact

Best regards,
Henrik Grimler

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Krzysztof Kozlowski]

On 09/09/2025 15:59, Anand Moon wrote:
> Hi Krzysztof, Marek,
> 
> On Tue, 30 Jul 2024 at 20:32, Anand Moon <linux.amoon@gmail.com> wrote:
>>
>> Hi Krzysztof,
>>
>> On Tue, 30 Jul 2024 at 18:53, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>
>>> On 30/07/2024 15:20, Anand Moon wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>>>>>
>>>>> On 30/07/2024 14:06, Anand Moon wrote:
>>>>>> Hi Marek,
>>>>>>
>>>>>> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 30.07.2024 11:13, Anand Moon wrote:
>>>>>>>> As per the Exynos 5422 user manual add missing cache information to
>>>>>>>> the Exynos542x SoC.
>>>>>>>>
>>>>>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
>>>>>>>>       32 KB of L1 data cache available.
>>>>>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
>>>>>>>>       32 KB of L1 data cache available.
>>>>>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
>>>>>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
>>>>>>>>
>>>>>>>> Features:
>>>>>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
>>>>>>>>    L2 cache snooping capability. This hardware automatic L2 cache
>>>>>>>>    snooping removes the efforts of synchronizing the contents of the
>>>>>>>>    two L2 caches in core switching event.
>>>>>>>>
>>>>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
>>>>>>>
>>>>>>>
>>>>>>> The provided values are not correct. Please refer to commit 5f41f9198f29
>>>>>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
>>>>>>> cores"), which adds workaround for different l1 icache line size between
>>>>>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
>>>>>>> boards.
>>>>>>>
>>>>>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
>>>>>> This patch is just updating the cache size for CPU for big.litle architecture..
>>>>>>
>>>>>
>>>>> Let me get it right. Marek's comment was that you used wrong values.
>>>>> Marek also provided rationale for this. Now your reply is that you
>>>>> update cache size? Sorry, I fail how you address Marek's comment.
>>>>>
>>>>> Do not repeat what the patch is doing. We all can see it. Instead
>>>>> respond to the comment with some sort of arguments.
>>>>>
>>>>
>>>> Ok, If I am not wrong  icache_size is hard-coded in the above commit.
>>>>
>>>> +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
>>>> +.globl icache_size
>>>> +       .data
>>>> +       .align  2
>>>> +icache_size:
>>>> +       .long   64
>>>> +       .text
>>>> +#endif
>>>>
>>>> In the check_cpu_icache_size function, we read the control reg
>>>> and recalculate the icache_size.
>>>> if there mismatch we re-apply the Icache_size,
>>>>
>>>> So dts passed values do not apply over here,
>>>
>>> So you provide incorrect values in terms of them being ignored? Then do
>>> not provide at all.
>>>
>> I will drop the icache and dcache values and just pass the L2_a7 and
>> L2_a15, value
>> Is this ok for you?
>>
>> Earlier, I have tried to verify this information in /sys and /proc
>> to verify the changes as ARM does not populate this information.
>>
> Here's an article that provides detailed insights into the cache feature.
> [0] http://jake.dothome.co.kr/cache4/

Here is Korean Wikipedia article about Sugar glider:
https://ko.wikipedia.org/wiki/%EC%9C%A0%EB%8C%80%ED%95%98%EB%8A%98%EB%8B%A4%EB%9E%8C%EC%A5%90

I guess we are putting now random references in Korean to our emails.


> 
> The values associated with L1 and L2 caches indicate their respective sizes,
> as specified in the ARM Technical Reference Manual (TRM) below.
> 
> Cortex-A15 L2 cache controller
> [0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller
> 
> Cortex-A7 L2 cache controller
> [1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller
> 
> These changes help define a fixed cache size, ensuring that active pages
> are mapped correctly within the expected cache boundaries.


As with many previous attempts, you do not understand comments and
questions and you do not reply to them. This makes conversation pointless.

To prove it:

1. No one asks for performance numbers.
2. You give performance numbers.

I am dropping this patch because you did not address actual comments. I
also do not plan to give thorough review to other of your patches,
because you wasted a lot of my time in the past and this example here
proves you keep wasting.

Best regards,
Krzysztof

Re: [PATCH v1 2/2] ARM: dts: samsung: Add cache information to the Exynos542x SoC

[Anand Moon]

Hi Krzysztof,

On Wed, 10 Sept 2025 at 12:46, Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 09/09/2025 15:59, Anand Moon wrote:
> > Hi Krzysztof, Marek,
> >
> > On Tue, 30 Jul 2024 at 20:32, Anand Moon <linux.amoon@gmail.com> wrote:
> >>
> >> Hi Krzysztof,
> >>
> >> On Tue, 30 Jul 2024 at 18:53, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>
> >>> On 30/07/2024 15:20, Anand Moon wrote:
> >>>> Hi Krzysztof,
> >>>>
> >>>> On Tue, 30 Jul 2024 at 17:57, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> >>>>>
> >>>>> On 30/07/2024 14:06, Anand Moon wrote:
> >>>>>> Hi Marek,
> >>>>>>
> >>>>>> On Tue, 30 Jul 2024 at 17:14, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> >>>>>>>
> >>>>>>>
> >>>>>>> On 30.07.2024 11:13, Anand Moon wrote:
> >>>>>>>> As per the Exynos 5422 user manual add missing cache information to
> >>>>>>>> the Exynos542x SoC.
> >>>>>>>>
> >>>>>>>> - Each Cortex-A7 core has 32 KB of instruction cache and
> >>>>>>>>       32 KB of L1 data cache available.
> >>>>>>>> - Each Cortex-A15 core has 32 KB of L1 instruction cache and
> >>>>>>>>       32 KB of L1 data cache available.
> >>>>>>>> - The little (A7) cluster has 512 KB of unified L2 cache available.
> >>>>>>>> - The big (A15) cluster has 2 MB of unified L2 cache available.
> >>>>>>>>
> >>>>>>>> Features:
> >>>>>>>> - Exynos 5422 support cache coherency interconnect (CCI) bus with
> >>>>>>>>    L2 cache snooping capability. This hardware automatic L2 cache
> >>>>>>>>    snooping removes the efforts of synchronizing the contents of the
> >>>>>>>>    two L2 caches in core switching event.
> >>>>>>>>
> >>>>>>>> Signed-off-by: Anand Moon <linux.amoon@gmail.com>
> >>>>>>>
> >>>>>>>
> >>>>>>> The provided values are not correct. Please refer to commit 5f41f9198f29
> >>>>>>> ("ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU
> >>>>>>> cores"), which adds workaround for different l1 icache line size between
> >>>>>>> big and little CPUs. This workaround gets enabled on all Exynos542x/5800
> >>>>>>> boards.
> >>>>>>>
> >>>>>> Ok, I have just referred to the Exynos 5422 user manual for this patch,
> >>>>>> This patch is just updating the cache size for CPU for big.litle architecture..
> >>>>>>
> >>>>>
> >>>>> Let me get it right. Marek's comment was that you used wrong values.
> >>>>> Marek also provided rationale for this. Now your reply is that you
> >>>>> update cache size? Sorry, I fail how you address Marek's comment.
> >>>>>
> >>>>> Do not repeat what the patch is doing. We all can see it. Instead
> >>>>> respond to the comment with some sort of arguments.
> >>>>>
> >>>>
> >>>> Ok, If I am not wrong  icache_size is hard-coded in the above commit.
> >>>>
> >>>> +#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND
> >>>> +.globl icache_size
> >>>> +       .data
> >>>> +       .align  2
> >>>> +icache_size:
> >>>> +       .long   64
> >>>> +       .text
> >>>> +#endif
> >>>>
> >>>> In the check_cpu_icache_size function, we read the control reg
> >>>> and recalculate the icache_size.
> >>>> if there mismatch we re-apply the Icache_size,
> >>>>
> >>>> So dts passed values do not apply over here,
> >>>
> >>> So you provide incorrect values in terms of them being ignored? Then do
> >>> not provide at all.
> >>>
> >> I will drop the icache and dcache values and just pass the L2_a7 and
> >> L2_a15, value
> >> Is this ok for you?
> >>
> >> Earlier, I have tried to verify this information in /sys and /proc
> >> to verify the changes as ARM does not populate this information.
> >>
> > Here's an article that provides detailed insights into the cache feature.
> > [0] http://jake.dothome.co.kr/cache4/
>
> Here is Korean Wikipedia article about Sugar glider:
> https://ko.wikipedia.org/wiki/%EC%9C%A0%EB%8C%80%ED%95%98%EB%8A%98%EB%8B%A4%EB%9E%8C%EC%A5%90
>
> I guess we are putting now random references in Korean to our emails.
>
That wasn’t my intention—I was simply trying to elaborate on my thought process.
If the reference came across as random or unclear,
I’ll make sure to be more precise going forward. Thanks for pointing it out.
>
> >
> > The values associated with L1 and L2 caches indicate their respective sizes,
> > as specified in the ARM Technical Reference Manual (TRM) below.
> >
> > Cortex-A15 L2 cache controller
> > [0] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a15-l2-cache-controller
> >
> > Cortex-A7 L2 cache controller
> > [1] https://developer.arm.com/documentation/ddi0503/i/programmers-model/programmable-peripherals-and-interfaces/cortex-a7-l2-cache-controller
> >
> > These changes help define a fixed cache size, ensuring that active pages
> > are mapped correctly within the expected cache boundaries.
>
>
> As with many previous attempts, you do not understand comments and
> questions and you do not reply to them. This makes conversation pointless.
>
> To prove it:
>
> 1. No one asks for performance numbers.
> 2. You give performance numbers.
>
I realize my explanation might have been confusing.
What I meant is that my changes take a different approach,
but they’re safe and don’t break the current codebase.

Specifically, they do not break or interfere with the behavior
introduced in commit
5f41f9198f29 ("ARM: 8864/1: Add workaround for I-Cache line size
mismatch between CPU cores").
> I am dropping this patch because you did not address actual comments. I
> also do not plan to give thorough review to other of your patches,
> because you wasted a lot of my time in the past and this example here
> proves you keep wasting.
Thanks for the feedback. I understand your frustration,
and I regret that my response didn’t adequately address your comments.
I intended to clarify my understanding and contribute constructively,
not to waste anyone’s time.

I’ll take this as a cue to improve how I respond to reviews going forward.
Appreciate the time you’ve spent engaging with my patches.
>
> Best regards,
> Krzysztof
Thanks
-Anand