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([2a01:e0a:f:6020:40ce:250c:1a13:d1ba]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e7607cd415sm6680739f8f.30.2025.09.12.07.14.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 12 Sep 2025 07:14:38 -0700 (PDT) From: Vincent Guittot To: chester62515@gmail.com, mbrugger@suse.com, ghennadi.procopciuc@oss.nxp.com, s32@nxp.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Ionut.Vicovan@nxp.com, larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com, ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/4] dt-bindings: pcie: Add the NXP PCIe controller Date: Fri, 12 Sep 2025 16:14:33 +0200 Message-ID: <20250912141436.2347852-2-vincent.guittot@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250912141436.2347852-1-vincent.guittot@linaro.org> References: <20250912141436.2347852-1-vincent.guittot@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250912_071440_978848_8316762F X-CRM114-Status: GOOD ( 20.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Describe the PCIe controller available on the S32G platforms. Co-developed-by: Ionut Vicovan Signed-off-by: Ionut Vicovan Co-developed-by: Bogdan-Gabriel Roman Signed-off-by: Bogdan-Gabriel Roman Co-developed-by: Larisa Grigore Signed-off-by: Larisa Grigore Co-developed-by: Ghennadi Procopciuc Signed-off-by: Ghennadi Procopciuc Co-developed-by: Ciprian Marian Costea Signed-off-by: Ciprian Marian Costea Co-developed-by: Bogdan Hamciuc Signed-off-by: Bogdan Hamciuc Signed-off-by: Vincent Guittot --- .../devicetree/bindings/pci/nxp,s32-pcie.yaml | 169 ++++++++++++++++++ 1 file changed, 169 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml new file mode 100644 index 000000000000..287596d7162d --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml @@ -0,0 +1,169 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/nxp,s32-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32G2xx/S32G3xx PCIe controller + +maintainers: + - Bogdan Hamciuc + - Ionut Vicovan + +description: + This PCIe controller is based on the Synopsys DesignWare PCIe IP. + The S32G SoC family has two PCIe controllers, which can be configured as + either Root Complex or End Point. + +properties: + compatible: + oneOf: + - enum: + - nxp,s32g2-pcie # S32G2 SoCs RC mode + - items: + - const: nxp,s32g3-pcie + - const: nxp,s32g2-pcie + + reg: + minItems: 7 + maxItems: 7 + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: dma + - const: ctrl + - const: config + - const: addr_space + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-names: + items: + - const: link_req_stat + - const: dma + - const: msi + - const: phy_link_down + - const: phy_link_up + - const: misc + - const: pcs + - const: tlp_req_no_comp + + msi-parent: + description: + Use this option to reference the GIC controller node which will + handle the MSIs. This property can be used only in Root Complex mode. + The msi-parent node must be declared as "msi-controller" and the list of + available SPIs that can be used must be declared using "mbi-ranges". + If "msi-parent" is not present in the PCIe node, MSIs will be handled + by iMSI-RX -Integrated MSI Receiver [AXI Bridge]-, an integrated + MSI reception module in the PCIe controller's AXI Bridge which + detects and terminates inbound MSI requests (received on the RX wire). + These MSIs no longer appear on the AXI bus, instead a hard-wired + interrupt is raised, documented as "DSP AXI MSI Interrupt" in the SoC + Reference Manual. + + nxp,phy-mode: + $ref: /schemas/types.yaml#/definitions/string + description: Select PHY mode for PCIe controller + enum: + - crns # Common Reference Clock, No Spread Spectrum + - crss # Common Reference Clock, Spread Spectrum + - srns # Separate reference Clock, No Spread Spectrum + - sris # Separate Reference Clock, Independent Spread Spectrum + + max-link-speed: + description: + The max link speed is normaly Gen3, but can be enforced to a lower value + in case of special limitations. + maximum: 3 + + num-lanes: + description: + Max bus width (1 or 2); it is the number of physical lanes + minimum: 1 + maximum: 2 + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-common.yaml# + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - ranges + - nxp,phy-mode + - num-lanes + - phys + +additionalProperties: true + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie0: pcie@40400000 { + compatible = "nxp,s32g3-pcie", + "nxp,s32g2-pcie"; + dma-coherent; + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */ + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */ + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */ + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */ + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */ + /* RC configuration space, 4KB each for cfg0 and cfg1 + * at the end of the outbound memory map + */ + <0x5f 0xffffe000 0x0 0x00002000>, + <0x58 0x00000000 0x0 0x40000000>; /* 1GB EP addr space */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", + "config", "addr_space"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = + /* downstream I/O, 64KB and aligned naturally just + * before the config space to minimize fragmentation + */ + <0x81000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>, + /* non-prefetchable memory, with best case size and + * alignment + */ + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>; + + nxp,phy-mode = "crns"; + bus-range = <0x0 0xff>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "link_req_stat", "dma", "msi", + "phy_link_down", "phy_link_up", "misc", + "pcs", "tlp_req_no_comp"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic 0 0 0 128 4>, + <0 0 0 2 &gic 0 0 0 129 4>, + <0 0 0 3 &gic 0 0 0 130 4>, + <0 0 0 4 &gic 0 0 0 131 4>; + msi-parent = <&gic>; + + num-lanes = <2>; + phys = <&serdes0 PHY_TYPE_PCIE 0 0>; + }; + }; -- 2.43.0