[PATCH 0/4] pcie: s32g: Add support for PCIe controller

Vincent Guittot
2025-09-12T14:14:48Z

The S32G SoC family has 2 PCIe controllers based on Designware IP.

Add the support for Host mode.

Ciprian Costea (1):
pcie: s32g: Add Phy clock definition

Vincent Guittot (3):
dt-bindings: pcie: Add the NXP PCIe controller
pcie: s32g: Add initial PCIe support (RC)
MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver

.../devicetree/bindings/pci/nxp,s32-pcie.yaml | 169 +++++
MAINTAINERS | 3 +
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pci-s32g-regs.h | 105 +++
drivers/pci/controller/dwc/pci-s32g.c | 697 ++++++++++++++++++
drivers/pci/controller/dwc/pci-s32g.h | 45 ++
.../linux/pcie/nxp-s32g-pcie-phy-submode.h | 15 +
8 files changed, 1047 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pci-s32g-regs.h
create mode 100644 drivers/pci/controller/dwc/pci-s32g.c
create mode 100644 drivers/pci/controller/dwc/pci-s32g.h
create mode 100644 include/linux/pcie/nxp-s32g-pcie-phy-submode.h

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2.43.0