Re: [PATCH 1/4] dt-bindings: pcie: Add the NXP PCIe controller

Bjorn Helgaas
2025-09-17T21:18:36Z

Suggest following convention for subject lines (run "git log --oneline
Documentation/devicetree/bindings/pci/"), e.g.,

dt-bindings: PCI: s32g: Add NXP PCIe controller

On Fri, Sep 12, 2025 at 04:14:33PM +0200, Vincent Guittot wrote:
> Describe the PCIe controller available on the S32G platforms.

> + pcie0: pcie@40400000 {
> + compatible = "nxp,s32g3-pcie",
> + "nxp,s32g2-pcie";
> + dma-coherent;
> + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi registers */
> + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 registers */
> + <0x00 0x40460000 0x0 0x00001000>, /* atu registers */
> + <0x00 0x40470000 0x0 0x00001000>, /* dma registers */
> + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl registers */
> + /* RC configuration space, 4KB each for cfg0 and cfg1
> + * at the end of the outbound memory map
> + */
> + <0x5f 0xffffe000 0x0 0x00002000>,
> + <0x58 0x00000000 0x0 0x40000000>; /* 1GB EP addr space */
> + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl",
> + "config", "addr_space";

Looks like an indentation error. Shouldn't "reg-names" and subsequent
properties be aligned under "reg"?

> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + ranges =
> + /* downstream I/O, 64KB and aligned naturally just
> + * before the config space to minimize fragmentation
> + */
> + <0x81000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>,
> + /* non-prefetchable memory, with best case size and
> + * alignment
> + */
> + <0x82000000 0x0 0x00000000 0x58 0x00000000 0x7 0xfffe0000>;
> +
> + nxp,phy-mode = "crns";

If "nxp,phy-mode" goes with "phys", should it be adjacent to it?

> + bus-range = <0x0 0xff>;
> + interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "link_req_stat", "dma", "msi",
> + "phy_link_down", "phy_link_up", "misc",
> + "pcs", "tlp_req_no_comp";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &gic 0 0 0 128 4>,
> + <0 0 0 2 &gic 0 0 0 129 4>,
> + <0 0 0 3 &gic 0 0 0 130 4>,
> + <0 0 0 4 &gic 0 0 0 131 4>;
> + msi-parent = <&gic>;
> +
> + num-lanes = <2>;
> + phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> + };
> + };