Re: [PATCH 1/4] dt-bindings: pcie: Add the NXP PCIe controller

Bjorn Helgaas
2025-09-16T14:23:24Z

On Tue, Sep 16, 2025 at 10:10:31AM +0200, Vincent Guittot wrote:
> On Sun, 14 Sept 2025 at 14:35, Vincent Guittot
> <vincent.guittot@linaro.org> wrote:
> > On Sat, 13 Sept 2025 at 00:50, Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > On Fri, Sep 12, 2025 at 04:14:33PM +0200, Vincent Guittot wrote:
> > > > Describe the PCIe controller available on the S32G platforms.

> > > > + num-lanes = <2>;
> > > > + phys = <&serdes0 PHY_TYPE_PCIE 0 0>;
> > >
> > > num-lanes and phys are properties of a Root Port, not the host bridge.
> > > Please put them in a separate stanza. See this for details and
> > > examples:
> > >
> > > https://lore.kernel.org/linux-pci/20250625221653.GA1590146@bhelgaas/
> >
> > Ok, I'm going to have a look
>
> This driver relies on dw_pcie_host_init() to get common resources like
> num-lane which doesn't look at childs to get num-lane.
>
> I have to keep num-lane in the pcie node. Having this in mind should I
> keep phys as well as they are both linked ?

Huh, that sounds like an issue in the DWC core. Jingoo, Mani?

dw_pcie_host_init() includes several things that assume a single Root
Port: num_lanes, of_pci_get_equalization_presets(),
dw_pcie_start_link() are all per-Root Port things.

Bjorn