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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v2 16/16] KVM: arm64: selftest: Expand external_aborts test to look for TTW levels
Date: Mon, 15 Sep 2025 12:44:51 +0100	[thread overview]
Message-ID: <20250915114451.660351-17-maz@kernel.org> (raw)
In-Reply-To: <20250915114451.660351-1-maz@kernel.org>

Add a basic test corrupting a level-2 table entry to check that
the resulting abort is a SEA on a PTW at level-3.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 .../selftests/kvm/arm64/external_aborts.c     | 43 +++++++++++++++++++
 .../selftests/kvm/include/arm64/processor.h   |  1 +
 .../selftests/kvm/lib/arm64/processor.c       | 13 +++++-
 3 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/tools/testing/selftests/kvm/arm64/external_aborts.c b/tools/testing/selftests/kvm/arm64/external_aborts.c
index 062bf84cced13..acb32d0f27bbe 100644
--- a/tools/testing/selftests/kvm/arm64/external_aborts.c
+++ b/tools/testing/selftests/kvm/arm64/external_aborts.c
@@ -250,6 +250,48 @@ static void test_serror(void)
 	kvm_vm_free(vm);
 }
 
+static void expect_sea_s1ptw_handler(struct ex_regs *regs)
+{
+	u64 esr = read_sysreg(esr_el1);
+
+
+	GUEST_ASSERT_EQ(regs->pc, expected_abort_pc);
+	GUEST_ASSERT_EQ(ESR_ELx_EC(esr), ESR_ELx_EC_DABT_CUR);
+	GUEST_ASSERT_EQ((esr & ESR_ELx_FSC), ESR_ELx_FSC_SEA_TTW(3));
+
+	GUEST_DONE();
+}
+
+static noinline void test_s1ptw_abort_guest(void)
+{
+	extern char test_s1ptw_abort_insn;
+
+	WRITE_ONCE(expected_abort_pc, (u64)&test_s1ptw_abort_insn);
+
+	asm volatile("test_s1ptw_abort_insn:\n\t"
+		     "ldr x0, [%0]\n\t"
+		     : : "r" (MMIO_ADDR) : "x0", "memory");
+
+	GUEST_FAIL("Load on S1PTW abort should not retire");
+}
+
+static void test_s1ptw_abort(void)
+{
+	struct kvm_vcpu *vcpu;
+	u64 *ptep, bad_pa;
+	struct kvm_vm *vm = vm_create_with_dabt_handler(&vcpu, test_s1ptw_abort_guest,
+							expect_sea_s1ptw_handler);
+
+	ptep = virt_get_pte_hva_at_level(vm, MMIO_ADDR, 2);
+	bad_pa = BIT(vm->pa_bits) - vm->page_size;
+
+	*ptep &= ~GENMASK(47, 12);
+	*ptep |= bad_pa;
+
+	vcpu_run_expect_done(vcpu);
+	kvm_vm_free(vm);
+}
+
 static void test_serror_emulated_guest(void)
 {
 	GUEST_ASSERT(!(read_sysreg(isr_el1) & ISR_EL1_A));
@@ -327,4 +369,5 @@ int main(void)
 	test_serror_masked();
 	test_serror_emulated();
 	test_mmio_ease();
+	test_s1ptw_abort();
 }
diff --git a/tools/testing/selftests/kvm/include/arm64/processor.h b/tools/testing/selftests/kvm/include/arm64/processor.h
index 255fed769a8a5..e3e916b1d9c4e 100644
--- a/tools/testing/selftests/kvm/include/arm64/processor.h
+++ b/tools/testing/selftests/kvm/include/arm64/processor.h
@@ -175,6 +175,7 @@ void vm_install_exception_handler(struct kvm_vm *vm,
 void vm_install_sync_handler(struct kvm_vm *vm,
 		int vector, int ec, handler_fn handler);
 
+uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level);
 uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva);
 
 static inline void cpu_relax(void)
diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/testing/selftests/kvm/lib/arm64/processor.c
index eb115123d7411..bd7480a93f963 100644
--- a/tools/testing/selftests/kvm/lib/arm64/processor.c
+++ b/tools/testing/selftests/kvm/lib/arm64/processor.c
@@ -185,7 +185,7 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
 	_virt_pg_map(vm, vaddr, paddr, attr_idx);
 }
 
-uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva)
+uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level)
 {
 	uint64_t *ptep;
 
@@ -195,17 +195,23 @@ uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva)
 	ptep = addr_gpa2hva(vm, vm->pgd) + pgd_index(vm, gva) * 8;
 	if (!ptep)
 		goto unmapped_gva;
+	if (level == 0)
+		return ptep;
 
 	switch (vm->pgtable_levels) {
 	case 4:
 		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8;
 		if (!ptep)
 			goto unmapped_gva;
+		if (level == 1)
+			break;
 		/* fall through */
 	case 3:
 		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8;
 		if (!ptep)
 			goto unmapped_gva;
+		if (level == 2)
+			break;
 		/* fall through */
 	case 2:
 		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8;
@@ -223,6 +229,11 @@ uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva)
 	exit(EXIT_FAILURE);
 }
 
+uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva)
+{
+	return virt_get_pte_hva_at_level(vm, gva, 3);
+}
+
 vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
 {
 	uint64_t *ptep = virt_get_pte_hva(vm, gva);
-- 
2.39.2



  parent reply	other threads:[~2025-09-15 11:45 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-15 11:44 [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 01/16] KVM: arm64: Add helper computing the state of 52bit PA support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 02/16] KVM: arm64: Account for 52bit when computing maximum OA Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 03/16] KVM: arm64: Compute 52bit TTBR address and alignment Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 04/16] KVM: arm64: Decouple output address from the PT descriptor Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 05/16] KVM: arm64: Pass the walk_info structure to compute_par_s1() Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 06/16] KVM: arm64: Compute shareability for LPA2 Marc Zyngier
2025-09-19 21:58   ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 07/16] KVM: arm64: Populate PAR_EL1 with 52bit addresses Marc Zyngier
2025-09-19 22:00   ` Oliver Upton
2025-09-20  9:27     ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 08/16] KVM: arm64: Expand valid block mappings to FEAT_LPA/LPA2 support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 09/16] KVM: arm64: Report faults from S1 walk setup at the expected start level Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 10/16] KVM: arm64: Allow use of S1 PTW for non-NV vcpus Marc Zyngier
2025-09-19 22:27   ` Oliver Upton
2025-09-20  9:24     ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 11/16] KVM: arm64: Allow EL1 control registers to be accessed from the CPU state Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 12/16] KVM: arm64: Don't switch MMU on translation from non-NV context Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 13/16] KVM: arm64: Add filtering hook to S1 page table walk Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 14/16] KVM: arm64: Add S1 IPA to page table level walker Marc Zyngier
2025-09-19 22:31   ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 15/16] KVM: arm64: Populate level on S1PTW SEA injection Marc Zyngier
2025-09-15 11:44 ` Marc Zyngier [this message]
2025-09-19 22:36   ` [PATCH v2 16/16] KVM: arm64: selftest: Expand external_aborts test to look for TTW levels Oliver Upton
2025-09-19 22:37 ` [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Oliver Upton
2025-09-21 11:00   ` Marc Zyngier
2025-09-21 10:57 ` Marc Zyngier

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