From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH v2 04/16] KVM: arm64: Decouple output address from the PT descriptor
Date: Mon, 15 Sep 2025 12:44:39 +0100 [thread overview]
Message-ID: <20250915114451.660351-5-maz@kernel.org> (raw)
In-Reply-To: <20250915114451.660351-1-maz@kernel.org>
Add a helper converting the descriptor into a nicely formed OA,
irrespective of the in-descriptor representation (< 52bit, LPA
or LPA2).
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/at.c | 30 +++++++++++++++++++++++++++---
1 file changed, 27 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c
index e02e467fc2ccd..bdb2c3e22f248 100644
--- a/arch/arm64/kvm/at.c
+++ b/arch/arm64/kvm/at.c
@@ -56,6 +56,29 @@ static bool has_52bit_pa(struct kvm_vcpu *vcpu, struct s1_walk_info *wi, u64 tcr
return (tcr & (wi->regime == TR_EL2 ? TCR_EL2_DS : TCR_DS));
}
+static u64 desc_to_oa(struct s1_walk_info *wi, u64 desc)
+{
+ u64 addr;
+
+ if (!wi->pa52bit)
+ return desc & GENMASK_ULL(47, wi->pgshift);
+
+ switch (BIT(wi->pgshift)) {
+ case SZ_4K:
+ case SZ_16K:
+ addr = desc & GENMASK_ULL(49, wi->pgshift);
+ addr |= FIELD_GET(KVM_PTE_ADDR_51_50_LPA2, desc) << 50;
+ break;
+ case SZ_64K:
+ default: /* IMPDEF: treat any other value as 64k */
+ addr = desc & GENMASK_ULL(47, wi->pgshift);
+ addr |= FIELD_GET(KVM_PTE_ADDR_51_48, desc) << 48;
+ break;
+ }
+
+ return addr;
+}
+
/* Return the translation regime that applies to an AT instruction */
static enum trans_regime compute_translation_regime(struct kvm_vcpu *vcpu, u32 op)
{
@@ -402,7 +425,7 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
wr->PXNTable |= FIELD_GET(PMD_TABLE_PXN, desc);
}
- baddr = desc & GENMASK_ULL(47, wi->pgshift);
+ baddr = desc_to_oa(wi, desc);
/* Check for out-of-range OA */
if (check_output_size(baddr, wi))
@@ -431,7 +454,8 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
goto transfault;
}
- if (check_output_size(desc & GENMASK(47, va_bottom), wi))
+ baddr = desc_to_oa(wi, desc);
+ if (check_output_size(baddr & GENMASK(52, va_bottom), wi))
goto addrsz;
if (!(desc & PTE_AF)) {
@@ -444,7 +468,7 @@ static int walk_s1(struct kvm_vcpu *vcpu, struct s1_walk_info *wi,
wr->failed = false;
wr->level = level;
wr->desc = desc;
- wr->pa = desc & GENMASK(47, va_bottom);
+ wr->pa = baddr & GENMASK(52, va_bottom);
wr->pa |= va & GENMASK_ULL(va_bottom - 1, 0);
wr->nG = (wi->regime != TR_EL2) && (desc & PTE_NG);
--
2.39.2
next prev parent reply other threads:[~2025-09-15 11:45 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 11:44 [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 01/16] KVM: arm64: Add helper computing the state of 52bit PA support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 02/16] KVM: arm64: Account for 52bit when computing maximum OA Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 03/16] KVM: arm64: Compute 52bit TTBR address and alignment Marc Zyngier
2025-09-15 11:44 ` Marc Zyngier [this message]
2025-09-15 11:44 ` [PATCH v2 05/16] KVM: arm64: Pass the walk_info structure to compute_par_s1() Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 06/16] KVM: arm64: Compute shareability for LPA2 Marc Zyngier
2025-09-19 21:58 ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 07/16] KVM: arm64: Populate PAR_EL1 with 52bit addresses Marc Zyngier
2025-09-19 22:00 ` Oliver Upton
2025-09-20 9:27 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 08/16] KVM: arm64: Expand valid block mappings to FEAT_LPA/LPA2 support Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 09/16] KVM: arm64: Report faults from S1 walk setup at the expected start level Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 10/16] KVM: arm64: Allow use of S1 PTW for non-NV vcpus Marc Zyngier
2025-09-19 22:27 ` Oliver Upton
2025-09-20 9:24 ` Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 11/16] KVM: arm64: Allow EL1 control registers to be accessed from the CPU state Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 12/16] KVM: arm64: Don't switch MMU on translation from non-NV context Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 13/16] KVM: arm64: Add filtering hook to S1 page table walk Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 14/16] KVM: arm64: Add S1 IPA to page table level walker Marc Zyngier
2025-09-19 22:31 ` Oliver Upton
2025-09-15 11:44 ` [PATCH v2 15/16] KVM: arm64: Populate level on S1PTW SEA injection Marc Zyngier
2025-09-15 11:44 ` [PATCH v2 16/16] KVM: arm64: selftest: Expand external_aborts test to look for TTW levels Marc Zyngier
2025-09-19 22:36 ` Oliver Upton
2025-09-19 22:37 ` [PATCH v2 00/16] KVM: arm64: TTW reporting on SEA and 52bit PA in S1 PTW Oliver Upton
2025-09-21 11:00 ` Marc Zyngier
2025-09-21 10:57 ` Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250915114451.660351-5-maz@kernel.org \
--to=maz@kernel.org \
--cc=joey.gouly@arm.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=oliver.upton@linux.dev \
--cc=suzuki.poulose@arm.com \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).