[PATCH v5 0/3] PCI: imx6: Add external reference clock mode support

[PATCH v5 0/3] PCI: imx6: Add external reference clock mode support

[Richard Zhu]

On i.MX, the PCIe reference clock might come from either internal system
PLL or external clock source. Add the external reference clock source
for reference clock.

Main change in v5:
- Update the commit message of first patch refer to Bejorn's comments.
- Correct the typo error and update the description of property in the
  first patch.

Main change in v4:
- Add one more reference clock "extref" to be onhalf the reference clock
  that comes from external crystal oscillator.
https://lore.kernel.org/imx/20250626073804.3113757-1-hongxing.zhu@nxp.com/

Main change in v3:
- Update the logic check external reference clock mode is enabled or
  not in the driver codes.
https://lore.kernel.org/imx/20250620031350.674442-1-hongxing.zhu@nxp.com/

Main change in v2:
- Fix yamllint warning.
- Refine the driver codes.
https://lore.kernel.org/imx/20250619091004.338419-1-hongxing.zhu@nxp.com/

[PATCH v5 1/3] dt-bindings: PCI: dwc: Add one more reference clock
[PATCH v5 2/3] dt-bindings: pci-imx6: Add external reference clock
[PATCH v5 3/3] PCI: imx6: Add external reference clock mode support

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml      |  7 ++++++-
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml |  6 ++++++
drivers/pci/controller/dwc/pci-imx6.c                          | 20 +++++++++++++-------
3 files changed, 25 insertions(+), 8 deletions(-)

[PATCH v5 1/3] dt-bindings: PCI: dwc: Add one more reference clock

[Richard Zhu]

Add one more reference clock "extref" to for a reference clock that
comes from external crystal oscillator.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 .../devicetree/bindings/pci/snps,dw-pcie-common.yaml        | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index 34594972d8db..0134a759185e 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -105,6 +105,12 @@ properties:
             define it with this name (for instance pipe, core and aux can
             be connected to a single source of the periodic signal).
           const: ref
+        - description:
+            Some dwc wrappers (like i.MX95 PCIes) have two reference clock
+            inputs, one from an internal PLL, the other from an off-chip crystal
+            oscillator. If present, 'extref' refers to a reference clock from
+            an external oscillator.
+          const: extref
         - description:
             Clock for the PHY registers interface. Originally this is
             a PHY-viewport-based interface, but some platform may have
-- 
2.37.1

[PATCH v5 2/3] dt-bindings: pci-imx6: Add external reference clock mode support

[Richard Zhu]

On i.MX, PCIe has two reference clock inputs: one from the internal PLL
and one from an external clock source. Only one needs to be used,
depending on the board design. Add the external reference clock source
for reference clock.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index ca5f2970f217..6be45abe6e52 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -219,7 +219,12 @@ allOf:
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
-            - const: ref
+            - description: PCIe reference clock.
+              oneOf:
+                - description: The controller has two reference clock
+                    inputs, internal system PLL and external clock
+                    source. Only one needs to be used.
+                  enum: [ref, extref]
 
 unevaluatedProperties: false
 
-- 
2.37.1

[PATCH v5 3/3] PCI: imx6: Add external reference clock mode support

[Richard Zhu]

The PCI Express reference clock of i.MX9 PCIes might come from external
clock source. Add the external reference clock mode support.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 5a38cfaf989b..9309959874c0 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -149,6 +149,7 @@ struct imx_pcie {
 	struct gpio_desc	*reset_gpiod;
 	struct clk_bulk_data	*clks;
 	int			num_clks;
+	bool			enable_ext_refclk;
 	struct regmap		*iomuxc_gpr;
 	u16			msi_ctrl;
 	u32			controller_id;
@@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+	bool ext = imx_pcie->enable_ext_refclk;
+
 	/*
 	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
 	 * Through Beacon or PERST# De-assertion
@@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 			IMX95_PCIE_PHY_CR_PARA_SEL,
 			IMX95_PCIE_PHY_CR_PARA_SEL);
 
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_PHY_GEN_CTRL,
-			   IMX95_PCIE_REF_USE_PAD, 0);
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_SS_RW_REG_0,
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+			   ext ? IMX95_PCIE_REF_USE_PAD : 0,
+			   IMX95_PCIE_REF_USE_PAD);
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
 			   IMX95_PCIE_REF_CLKEN,
-			   IMX95_PCIE_REF_CLKEN);
+			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
 
 	return 0;
 }
@@ -1600,7 +1602,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	struct imx_pcie *imx_pcie;
 	struct device_node *np;
 	struct device_node *node = dev->of_node;
-	int ret, domain;
+	int i, ret, domain;
 	u16 val;
 
 	imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1651,6 +1653,10 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	if (imx_pcie->num_clks < 0)
 		return dev_err_probe(dev, imx_pcie->num_clks,
 				     "failed to get clocks\n");
+	imx_pcie->enable_ext_refclk = true;
+	for (i = 0; i < imx_pcie->num_clks; i++)
+		if (strncmp(imx_pcie->clks[i].id, "ref", 3) == 0)
+			imx_pcie->enable_ext_refclk = false;
 
 	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
 		imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
-- 
2.37.1

Re: [PATCH v5 1/3] dt-bindings: PCI: dwc: Add one more reference clock

[Frank Li]

On Mon, Sep 15, 2025 at 11:53:46AM +0800, Richard Zhu wrote:
> Add one more reference clock "extref" to for a reference clock that
> comes from external crystal oscillator.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
>  .../devicetree/bindings/pci/snps,dw-pcie-common.yaml        | 6 ++++++
>  1 file changed, 6 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index 34594972d8db..0134a759185e 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -105,6 +105,12 @@ properties:
>              define it with this name (for instance pipe, core and aux can
>              be connected to a single source of the periodic signal).
>            const: ref
> +        - description:
> +            Some dwc wrappers (like i.MX95 PCIes) have two reference clock
> +            inputs, one from an internal PLL, the other from an off-chip crystal
> +            oscillator. If present, 'extref' refers to a reference clock from
> +            an external oscillator.
> +          const: extref
>          - description:
>              Clock for the PHY registers interface. Originally this is
>              a PHY-viewport-based interface, but some platform may have
> --
> 2.37.1
>

Re: [PATCH v5 2/3] dt-bindings: pci-imx6: Add external reference clock mode support

[Rob Herring]

On Mon, Sep 15, 2025 at 11:53:47AM +0800, Richard Zhu wrote:
> On i.MX, PCIe has two reference clock inputs: one from the internal PLL
> and one from an external clock source. Only one needs to be used,
> depending on the board design. Add the external reference clock source
> for reference clock.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
>  1 file changed, 6 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> index ca5f2970f217..6be45abe6e52 100644
> --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> @@ -219,7 +219,12 @@ allOf:
>              - const: pcie_bus
>              - const: pcie_phy
>              - const: pcie_aux
> -            - const: ref
> +            - description: PCIe reference clock.
> +              oneOf:
> +                - description: The controller has two reference clock
> +                    inputs, internal system PLL and external clock
> +                    source. Only one needs to be used.
> +                  enum: [ref, extref]

This seems wrong to me. There's still only 1 ref input to the PCIe 
block. If you had 10 possible choices for the ref clock source, would 
you add 10 clock names here? No!

Can't you detect what the parent clock is for the 'ref' clock? and 
configure the GPR register appropriately. Or that mux should be modeled 
as a clock provider.

Rob

RE: [PATCH v5 2/3] dt-bindings: pci-imx6: Add external reference clock mode support

[Hongxing Zhu]

> -----Original Message-----
> From: Rob Herring <robh@kernel.org>
> Sent: 2025年9月22日 23:51
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> kwilczynski@kernel.org; mani@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; bhelgaas@google.com; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v5 2/3] dt-bindings: pci-imx6: Add external reference clock
> mode support
> 
> On Mon, Sep 15, 2025 at 11:53:47AM +0800, Richard Zhu wrote:
> > On i.MX, PCIe has two reference clock inputs: one from the internal
> > PLL and one from an external clock source. Only one needs to be used,
> > depending on the board design. Add the external reference clock source
> > for reference clock.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index ca5f2970f217..6be45abe6e52 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -219,7 +219,12 @@ allOf:
> >              - const: pcie_bus
> >              - const: pcie_phy
> >              - const: pcie_aux
> > -            - const: ref
> > +            - description: PCIe reference clock.
> > +              oneOf:
> > +                - description: The controller has two reference clock
> > +                    inputs, internal system PLL and external clock
> > +                    source. Only one needs to be used.
> > +                  enum: [ref, extref]
> 
> This seems wrong to me. There's still only 1 ref input to the PCIe block. If you
> had 10 possible choices for the ref clock source, would you add 10 clock names
> here? No!
> 
> Can't you detect what the parent clock is for the 'ref' clock? and configure the
> GPR register appropriately. Or that mux should be modeled as a clock provider.
Hi Rob:
Thanks for your concerns.
Per to the discussion about clock source.
https://lore.kernel.org/imx/aGKm41I%2FFsrWN8jN@lizhi-Precision-Tower-5810/
There are two clock sources on i.MX95 PCIe.

Best Regards
Richard Zhu
> 
> Rob

Re: [PATCH v5 2/3] dt-bindings: pci-imx6: Add external reference clock mode support

[Frank Li]

On Mon, Sep 22, 2025 at 10:50:54AM -0500, Rob Herring wrote:
> On Mon, Sep 15, 2025 at 11:53:47AM +0800, Richard Zhu wrote:
> > On i.MX, PCIe has two reference clock inputs: one from the internal PLL
> > and one from an external clock source. Only one needs to be used,
> > depending on the board design. Add the external reference clock source
> > for reference clock.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > Reviewed-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 7 ++++++-
> >  1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > index ca5f2970f217..6be45abe6e52 100644
> > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
> > @@ -219,7 +219,12 @@ allOf:
> >              - const: pcie_bus
> >              - const: pcie_phy
> >              - const: pcie_aux
> > -            - const: ref
> > +            - description: PCIe reference clock.
> > +              oneOf:
> > +                - description: The controller has two reference clock
> > +                    inputs, internal system PLL and external clock
> > +                    source. Only one needs to be used.
> > +                  enum: [ref, extref]
>
> This seems wrong to me. There's still only 1 ref input to the PCIe
> block. If you had 10 possible choices for the ref clock source, would
> you add 10 clock names here? No!
>
> Can't you detect what the parent clock is for the 'ref' clock?

In include/linux/clk.h, I have not found any API to get clk providor's
information. let me know if I missed it.

> and
> configure the GPR register appropriately. Or that mux should be modeled
> as a clock provider.

The mux is inside PCIe controller IP. Similar case in S32 RTC, which have
4 clk inputs and mux is inside IP.

https://lore.kernel.org/all/20241104152934.GA129622-robh@kernel.org/

We met many similar cases. Actually s32 rtc's first version modeled as
clock provider, but this way is rejected because no clock output.

Frank

>
> Rob