[PATCH v7 0/3] PCI: imx6: Add external reference clock mode support

[PATCH v7 0/3] PCI: imx6: Add external reference clock mode support

[Richard Zhu]

i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.

Add external reference clock input mode support for i.MX95 PCIes.

Main change in v7:
- Refine the subjects and commit message refer to Bjorn's comments.

Main change in v6:
- Refer to Krzysztof's comments, let i.MX95 PCIes has the "ref" clock
  since it is wired actually, and add one more optional "extref" clock
  for i.MX95 PCIes.
https://lore.kernel.org/imx/20250917045238.1048484-1-hongxing.zhu@nxp.com/

Main change in v5:
- Update the commit message of first patch refer to Bejorn's comments.
- Correct the typo error and update the description of property in the
  first patch.
https://lore.kernel.org/imx/20250915035348.3252353-1-hongxing.zhu@nxp.com/

Main change in v4:
- Add one more reference clock "extref" to be onhalf the reference clock
  that comes from external crystal oscillator.
https://lore.kernel.org/imx/20250626073804.3113757-1-hongxing.zhu@nxp.com/

Main change in v3:
- Update the logic check external reference clock mode is enabled or
  not in the driver codes.
https://lore.kernel.org/imx/20250620031350.674442-1-hongxing.zhu@nxp.com/

Main change in v2:
- Fix yamllint warning.
- Refine the driver codes.
https://lore.kernel.org/imx/20250619091004.338419-1-hongxing.zhu@nxp.com/

[PATCH v7 1/3] dt-bindings: PCI: dwc: Add external reference clock
[PATCH v7 2/3] dt-bindings: PCI: pci-imx6: Add external reference
[PATCH v7 3/3] PCI: imx6: Add external reference clock input mode

Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml      |  3 +++
Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml |  6 ++++++
drivers/pci/controller/dwc/pci-imx6.c                          | 20 +++++++++++++-------
3 files changed, 22 insertions(+), 7 deletions(-)

[PATCH v7 1/3] dt-bindings: PCI: dwc: Add external reference clock input

[Richard Zhu]

Add external reference clock input "extref" for a reference clock that
comes from external crystal oscillator.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 .../devicetree/bindings/pci/snps,dw-pcie-common.yaml        | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
index 34594972d8db..0134a759185e 100644
--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
+++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
@@ -105,6 +105,12 @@ properties:
             define it with this name (for instance pipe, core and aux can
             be connected to a single source of the periodic signal).
           const: ref
+        - description:
+            Some dwc wrappers (like i.MX95 PCIes) have two reference clock
+            inputs, one from an internal PLL, the other from an off-chip crystal
+            oscillator. If present, 'extref' refers to a reference clock from
+            an external oscillator.
+          const: extref
         - description:
             Clock for the PHY registers interface. Originally this is
             a PHY-viewport-based interface, but some platform may have
-- 
2.37.1

[PATCH v7 2/3] dt-bindings: PCI: pci-imx6: Add external reference clock input

[Richard Zhu]

i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.

Add external reference clock input for i.MX95 PCIes.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index ca5f2970f217..b4c40d0573dc 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -212,14 +212,17 @@ allOf:
     then:
       properties:
         clocks:
+          minItems: 4
           maxItems: 5
         clock-names:
+          minItems: 4
           items:
             - const: pcie
             - const: pcie_bus
             - const: pcie_phy
             - const: pcie_aux
             - const: ref
+            - const: extref  # Optional
 
 unevaluatedProperties: false
 
-- 
2.37.1

[PATCH v7 3/3] PCI: imx6: Add external reference clock input mode support

[Richard Zhu]

i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
other from off chip crystal oscillator. The "extref" clock refers to a
reference clock from an external crystal oscillator.

Add external reference clock input mode support for i.MX95 PCIes.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
 drivers/pci/controller/dwc/pci-imx6.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 80e48746bbaf..e2ca8b036253 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -149,6 +149,7 @@ struct imx_pcie {
 	struct gpio_desc	*reset_gpiod;
 	struct clk_bulk_data	*clks;
 	int			num_clks;
+	bool			enable_ext_refclk;
 	struct regmap		*iomuxc_gpr;
 	u16			msi_ctrl;
 	u32			controller_id;
@@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
 
 static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 {
+	bool ext = imx_pcie->enable_ext_refclk;
+
 	/*
 	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
 	 * Through Beacon or PERST# De-assertion
@@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
 			IMX95_PCIE_PHY_CR_PARA_SEL,
 			IMX95_PCIE_PHY_CR_PARA_SEL);
 
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_PHY_GEN_CTRL,
-			   IMX95_PCIE_REF_USE_PAD, 0);
-	regmap_update_bits(imx_pcie->iomuxc_gpr,
-			   IMX95_PCIE_SS_RW_REG_0,
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
+			   ext ? IMX95_PCIE_REF_USE_PAD : 0,
+			   IMX95_PCIE_REF_USE_PAD);
+	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
 			   IMX95_PCIE_REF_CLKEN,
-			   IMX95_PCIE_REF_CLKEN);
+			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
 
 	return 0;
 }
@@ -1606,7 +1608,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	struct imx_pcie *imx_pcie;
 	struct device_node *np;
 	struct device_node *node = dev->of_node;
-	int ret, domain;
+	int i, ret, domain;
 	u16 val;
 
 	imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
@@ -1657,6 +1659,10 @@ static int imx_pcie_probe(struct platform_device *pdev)
 	if (imx_pcie->num_clks < 0)
 		return dev_err_probe(dev, imx_pcie->num_clks,
 				     "failed to get clocks\n");
+	imx_pcie->enable_ext_refclk = false;
+	for (i = 0; i < imx_pcie->num_clks; i++)
+		if (strncmp(imx_pcie->clks[i].id, "extref", 6) == 0)
+			imx_pcie->enable_ext_refclk = true;
 
 	if (imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_PHYDRV)) {
 		imx_pcie->phy = devm_phy_get(dev, "pcie-phy");
-- 
2.37.1

Re: [PATCH v7 3/3] PCI: imx6: Add external reference clock input mode support

[Manivannan Sadhasivam]

On Thu, Sep 18, 2025 at 11:25:55AM +0800, Richard Zhu wrote:
> i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
> other from off chip crystal oscillator. The "extref" clock refers to a
> reference clock from an external crystal oscillator.
> 
> Add external reference clock input mode support for i.MX95 PCIes.
> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c | 20 +++++++++++++-------
>  1 file changed, 13 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 80e48746bbaf..e2ca8b036253 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -149,6 +149,7 @@ struct imx_pcie {
>  	struct gpio_desc	*reset_gpiod;
>  	struct clk_bulk_data	*clks;
>  	int			num_clks;
> +	bool			enable_ext_refclk;
>  	struct regmap		*iomuxc_gpr;
>  	u16			msi_ctrl;
>  	u32			controller_id;
> @@ -241,6 +242,8 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie)
>  
>  static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  {
> +	bool ext = imx_pcie->enable_ext_refclk;
> +
>  	/*
>  	 * ERR051624: The Controller Without Vaux Cannot Exit L23 Ready
>  	 * Through Beacon or PERST# De-assertion
> @@ -259,13 +262,12 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie)
>  			IMX95_PCIE_PHY_CR_PARA_SEL,
>  			IMX95_PCIE_PHY_CR_PARA_SEL);
>  
> -	regmap_update_bits(imx_pcie->iomuxc_gpr,
> -			   IMX95_PCIE_PHY_GEN_CTRL,
> -			   IMX95_PCIE_REF_USE_PAD, 0);
> -	regmap_update_bits(imx_pcie->iomuxc_gpr,
> -			   IMX95_PCIE_SS_RW_REG_0,
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_GEN_CTRL,
> +			   ext ? IMX95_PCIE_REF_USE_PAD : 0,
> +			   IMX95_PCIE_REF_USE_PAD);
> +	regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_0,
>  			   IMX95_PCIE_REF_CLKEN,
> -			   IMX95_PCIE_REF_CLKEN);
> +			   ext ? 0 : IMX95_PCIE_REF_CLKEN);
>  
>  	return 0;
>  }
> @@ -1606,7 +1608,7 @@ static int imx_pcie_probe(struct platform_device *pdev)
>  	struct imx_pcie *imx_pcie;
>  	struct device_node *np;
>  	struct device_node *node = dev->of_node;
> -	int ret, domain;
> +	int i, ret, domain;
>  	u16 val;
>  
>  	imx_pcie = devm_kzalloc(dev, sizeof(*imx_pcie), GFP_KERNEL);
> @@ -1657,6 +1659,10 @@ static int imx_pcie_probe(struct platform_device *pdev)
>  	if (imx_pcie->num_clks < 0)
>  		return dev_err_probe(dev, imx_pcie->num_clks,
>  				     "failed to get clocks\n");
> +	imx_pcie->enable_ext_refclk = false;

Default value is 'false'. So no need to initialize.

- Mani

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 0/3] PCI: imx6: Add external reference clock mode support

[Manivannan Sadhasivam]

On Thu, Sep 18, 2025 at 11:25:52AM +0800, Richard Zhu wrote:
> i.MX95 PCIes have two reference clock inputs: one from internal PLL, the
> other from off chip crystal oscillator. The "extref" clock refers to a
> reference clock from an external crystal oscillator.
> 
> Add external reference clock input mode support for i.MX95 PCIes.
> 

Driver change looks good to me (except a nitpick that I reported, but I could
fix it while applying), but the binding patches need to be reviewed by the DT
binding maintainers.

- Mani

> Main change in v7:
> - Refine the subjects and commit message refer to Bjorn's comments.
> 
> Main change in v6:
> - Refer to Krzysztof's comments, let i.MX95 PCIes has the "ref" clock
>   since it is wired actually, and add one more optional "extref" clock
>   for i.MX95 PCIes.
> https://lore.kernel.org/imx/20250917045238.1048484-1-hongxing.zhu@nxp.com/
> 
> Main change in v5:
> - Update the commit message of first patch refer to Bejorn's comments.
> - Correct the typo error and update the description of property in the
>   first patch.
> https://lore.kernel.org/imx/20250915035348.3252353-1-hongxing.zhu@nxp.com/
> 
> Main change in v4:
> - Add one more reference clock "extref" to be onhalf the reference clock
>   that comes from external crystal oscillator.
> https://lore.kernel.org/imx/20250626073804.3113757-1-hongxing.zhu@nxp.com/
> 
> Main change in v3:
> - Update the logic check external reference clock mode is enabled or
>   not in the driver codes.
> https://lore.kernel.org/imx/20250620031350.674442-1-hongxing.zhu@nxp.com/
> 
> Main change in v2:
> - Fix yamllint warning.
> - Refine the driver codes.
> https://lore.kernel.org/imx/20250619091004.338419-1-hongxing.zhu@nxp.com/
> 
> [PATCH v7 1/3] dt-bindings: PCI: dwc: Add external reference clock
> [PATCH v7 2/3] dt-bindings: PCI: pci-imx6: Add external reference
> [PATCH v7 3/3] PCI: imx6: Add external reference clock input mode
> 
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml      |  3 +++
> Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml |  6 ++++++
> drivers/pci/controller/dwc/pci-imx6.c                          | 20 +++++++++++++-------
> 3 files changed, 22 insertions(+), 7 deletions(-)
> 

-- 
மணிவண்ணன் சதாசிவம்

RE: [PATCH v7 0/3] PCI: imx6: Add external reference clock mode support

[Hongxing Zhu]

> -----Original Message-----
> From: Manivannan Sadhasivam <mani@kernel.org>
> Sent: 2025年9月20日 15:39
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: Frank Li <frank.li@nxp.com>; l.stach@pengutronix.de; lpieralisi@kernel.org;
> kwilczynski@kernel.org; robh@kernel.org; krzk+dt@kernel.org;
> conor+dt@kernel.org; bhelgaas@google.com; shawnguo@kernel.org;
> s.hauer@pengutronix.de; kernel@pengutronix.de; festevam@gmail.com;
> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> devicetree@vger.kernel.org; imx@lists.linux.dev; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v7 0/3] PCI: imx6: Add external reference clock mode
> support
> 
> On Thu, Sep 18, 2025 at 11:25:52AM +0800, Richard Zhu wrote:
> > i.MX95 PCIes have two reference clock inputs: one from internal PLL,
> > the other from off chip crystal oscillator. The "extref" clock refers
> > to a reference clock from an external crystal oscillator.
> >
> > Add external reference clock input mode support for i.MX95 PCIes.
> >
> 
> Driver change looks good to me (except a nitpick that I reported, but I could fix
> it while applying), but the binding patches need to be reviewed by the DT
> binding maintainers.
Hi Mani:
Thanks a lot for your kindly help.

Hi Krzysztof:
Can you help to take a look at the first two dt-binding patches?
Sorry to send out this patch-set late, because that I mis-understood
 what's your means in the previous review around.

Best Regards
Richard Zhu
> 
> - Mani
> 
> > Main change in v7:
> > - Refine the subjects and commit message refer to Bjorn's comments.
> >
> > Main change in v6:
> > - Refer to Krzysztof's comments, let i.MX95 PCIes has the "ref" clock
> >   since it is wired actually, and add one more optional "extref" clock
> >   for i.MX95 PCIes.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250917045238.1048484-1-hongxing.zhu%40nxp.co
> m%2F
> >
> &data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008d
> df818c
> >
> 705%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63893950749741
> 1261%7C
> >
> Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlAi
> >
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=B
> Gjzm9
> > %2FClFXNW9cMNYXIps6LwwxBx%2FX%2BzX%2B1Njijw20%3D&reserved=0
> >
> > Main change in v5:
> > - Update the commit message of first patch refer to Bejorn's comments.
> > - Correct the typo error and update the description of property in the
> >   first patch.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250915035348.3252353-1-hongxing.zhu%40nxp.co
> m%2F
> >
> &data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008d
> df818c
> >
> 705%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63893950749743
> 6951%7C
> >
> Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlAi
> >
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=S
> NH5kT
> > uJ2Qj1WWRD%2FomjWS1nZOxSjcw1of%2FWG2LPayc%3D&reserved=0
> >
> > Main change in v4:
> > - Add one more reference clock "extref" to be onhalf the reference clock
> >   that comes from external crystal oscillator.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250626073804.3113757-1-hongxing.zhu%40nxp.co
> m%2F
> >
> &data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008d
> df818c
> >
> 705%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C63893950749745
> 2416%7C
> >
> Unknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAw
> MCIsIlAi
> >
> OiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=8
> jduPW
> > G2eNaO2DH3yQfIP2JM%2F3GNcR3HeXJYD3FWX2I%3D&reserved=0
> >
> > Main change in v3:
> > - Update the logic check external reference clock mode is enabled or
> >   not in the driver codes.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250620031350.674442-1-hongxing.zhu%40nxp.com
> %2F&
> >
> data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008ddf
> 818c7
> >
> 05%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638939507497467
> 169%7CU
> >
> nknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwM
> CIsIlAiO
> >
> iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=iK
> wlgqy
> > k9mtl6n48E8mwPLXw1kWMtatc3j084TEqePM%3D&reserved=0
> >
> > Main change in v2:
> > - Fix yamllint warning.
> > - Refine the driver codes.
> > https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore
> > .kernel.org%2Fimx%2F20250619091004.338419-1-hongxing.zhu%40nxp.com
> %2F&
> >
> data=05%7C02%7Chongxing.zhu%40nxp.com%7C296faa4d1fc144046ce008ddf
> 818c7
> >
> 05%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638939507497482
> 698%7CU
> >
> nknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwM
> CIsIlAiO
> >
> iJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=AS
> vy6X%
> > 2BYrzeyjoAvtGBxHu3lBwMXmSvIqdUEDSofIhc%3D&reserved=0
> >
> > [PATCH v7 1/3] dt-bindings: PCI: dwc: Add external reference clock
> > [PATCH v7 2/3] dt-bindings: PCI: pci-imx6: Add external reference
> > [PATCH v7 3/3] PCI: imx6: Add external reference clock input mode
> >
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml      |  3 +++
> > Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml |  6
> ++++++
> > drivers/pci/controller/dwc/pci-imx6.c                          | 20
> +++++++++++++-------
> > 3 files changed, 22 insertions(+), 7 deletions(-)
> >
> 
> --
> மணிவண்ணன் சதாசிவம்

Re: [PATCH v7 1/3] dt-bindings: PCI: dwc: Add external reference clock input

[Rob Herring]

On Thu, Sep 18, 2025 at 11:25:53AM +0800, Richard Zhu wrote:
> Add external reference clock input "extref" for a reference clock that
> comes from external crystal oscillator.

Sigh. A different subject on every version throws off my scripts... 
Perhaps slow down your pace of sending new versions.

See my comments on v5.

> 
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> ---
>  .../devicetree/bindings/pci/snps,dw-pcie-common.yaml        | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> index 34594972d8db..0134a759185e 100644
> --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
> @@ -105,6 +105,12 @@ properties:
>              define it with this name (for instance pipe, core and aux can
>              be connected to a single source of the periodic signal).
>            const: ref
> +        - description:
> +            Some dwc wrappers (like i.MX95 PCIes) have two reference clock
> +            inputs, one from an internal PLL, the other from an off-chip crystal
> +            oscillator. If present, 'extref' refers to a reference clock from
> +            an external oscillator.
> +          const: extref
>          - description:
>              Clock for the PHY registers interface. Originally this is
>              a PHY-viewport-based interface, but some platform may have
> -- 
> 2.37.1
>