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From: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
To: AngeloGioacchino Del Regno
	<angelogioacchino.delregno@collabora.com>,
	 Boris Brezillon <boris.brezillon@collabora.com>,
	 Jassi Brar <jassisinghbrar@gmail.com>,
	Chia-I Wu <olvaffe@gmail.com>,  Chen-Yu Tsai <wenst@chromium.org>,
	Steven Price <steven.price@arm.com>,
	 Liviu Dudau <liviu.dudau@arm.com>,
	 Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	 Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>,  Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	 Matthias Brugger <matthias.bgg@gmail.com>,
	Kees Cook <kees@kernel.org>,
	 "Gustavo A. R. Silva" <gustavoars@kernel.org>,
	 Ulf Hansson <ulf.hansson@linaro.org>
Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org,
	 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 linux-arm-kernel@lists.infradead.org,
	linux-mediatek@lists.infradead.org,
	 linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org,
	 Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Subject: [PATCH v4 1/8] dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant
Date: Tue, 23 Sep 2025 13:39:54 +0200	[thread overview]
Message-ID: <20250923-mt8196-gpufreq-v4-1-6cd63ade73d6@collabora.com> (raw)
In-Reply-To: <20250923-mt8196-gpufreq-v4-0-6cd63ade73d6@collabora.com>

The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to
control the power and frequency of the GPU. This is modelled as a power
domain and clock provider.

It lets us omit the OPP tables from the device tree, as those can now be
enumerated at runtime from the MCU.

Add the necessary schema logic to handle what this SoC expects in terms
of clocks and power-domains.

Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
---
 .../bindings/gpu/arm,mali-valhall-csf.yaml         | 40 ++++++++++++++++++++--
 1 file changed, 38 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
index 7ad5a3ffc5f5c753322eda9e74cc65de89d11c73..860691ce985e560536b6c515b82441ba6d367c46 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
@@ -45,7 +45,9 @@ properties:
     minItems: 1
     items:
       - const: core
-      - const: coregroup
+      - enum:
+          - coregroup
+          - stacks
       - const: stacks
 
   mali-supply: true
@@ -92,7 +94,6 @@ required:
   - interrupts
   - interrupt-names
   - clocks
-  - mali-supply
 
 additionalProperties: false
 
@@ -109,6 +110,29 @@ allOf:
         power-domains:
           maxItems: 1
         power-domain-names: false
+      required:
+        - mali-supply
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: mediatek,mt8196-mali
+    then:
+      properties:
+        mali-supply: false
+        sram-supply: false
+        operating-points-v2: false
+        power-domains:
+          maxItems: 1
+        power-domain-names: false
+        clocks:
+          maxItems: 2
+        clock-names:
+          items:
+            - const: core
+            - const: stacks
+      required:
+        - power-domains
 
 examples:
   - |
@@ -144,5 +168,17 @@ examples:
             };
         };
     };
+  - |
+    gpu@48000000 {
+        compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
+        reg = <0x48000000 0x480000>;
+        clocks = <&gpufreq 0>, <&gpufreq 1>;
+        clock-names = "core", "stacks";
+        interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
+                     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
+                     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
+        interrupt-names = "job", "mmu", "gpu";
+        power-domains = <&gpufreq>;
+    };
 
 ...

-- 
2.51.0



  reply	other threads:[~2025-09-23 11:40 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-23 11:39 [PATCH v4 0/8] MT8196 GPU Frequency/Power Control Support Nicolas Frattaroli
2025-09-23 11:39 ` Nicolas Frattaroli [this message]
2025-09-23 11:39 ` [PATCH v4 2/8] dt-bindings: power: Add MT8196 GPU frequency control binding Nicolas Frattaroli
2025-09-24 11:30   ` AngeloGioacchino Del Regno
2025-09-23 11:39 ` [PATCH v4 3/8] dt-bindings: sram: Add compatible for mediatek,mt8196-gpufreq-sram Nicolas Frattaroli
2025-09-23 11:39 ` [PATCH v4 4/8] dt-bindings: mailbox: Add MT8196 GPUEB Mailbox Nicolas Frattaroli
2025-09-23 14:39   ` Rob Herring (Arm)
2025-09-23 11:39 ` [PATCH v4 5/8] mailbox: add MediaTek GPUEB IPI mailbox Nicolas Frattaroli
2025-09-24 11:35   ` AngeloGioacchino Del Regno
2025-09-23 11:39 ` [PATCH v4 6/8] drm/panthor: call into devfreq for current frequency Nicolas Frattaroli
2025-09-23 11:40 ` [PATCH v4 7/8] drm/panthor: Use existing OPP table if present Nicolas Frattaroli
2025-09-23 11:40 ` [PATCH v4 8/8] pmdomain: mediatek: Add support for MFlexGraphics Nicolas Frattaroli
2025-09-23 14:24   ` Ulf Hansson
2025-09-25 14:04     ` Nicolas Frattaroli
2025-09-29  9:58       ` Ulf Hansson
2025-09-23 16:25   ` AngeloGioacchino Del Regno
2025-09-24 19:11     ` Nicolas Frattaroli
2025-09-25 13:56       ` AngeloGioacchino Del Regno

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