[PATCH v2 1/2] dt-bindings: arm64: dts: airoha: Add AN7583 compatible

[PATCH v2 1/2] dt-bindings: arm64: dts: airoha: Add AN7583 compatible

[Christian Marangi]

Add Airoha AN7583 compatible to the list of enum for Airoha Supported
SoCs.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v2:
- Follow alphabetical order

 Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml
index 7c38c08dbf3f..df897227b870 100644
--- a/Documentation/devicetree/bindings/arm/airoha.yaml
+++ b/Documentation/devicetree/bindings/arm/airoha.yaml
@@ -18,6 +18,10 @@ properties:
     const: '/'
   compatible:
     oneOf:
+      - items:
+          - enum:
+              - airoha,an7583-evb
+          - const: airoha,an7583
       - items:
           - enum:
               - airoha,en7523-evb
-- 
2.51.0

[PATCH v2 2/2] arm64: dts: Add Airoha AN7583 SoC and AN7583 Evaluation Board

[Christian Marangi]

Introduce Airoha AN7583 SoC initial DTSI and AN7583 Evaluation Board
DTS and add the required entry in the Makefile.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
Changes v2:
- Fix DTB BOT warning (fix crypto compatible and OPP node name)

 arch/arm64/boot/dts/airoha/Makefile       |   1 +
 arch/arm64/boot/dts/airoha/an7583-evb.dts |  22 ++
 arch/arm64/boot/dts/airoha/an7583.dtsi    | 282 ++++++++++++++++++++++
 3 files changed, 305 insertions(+)
 create mode 100644 arch/arm64/boot/dts/airoha/an7583-evb.dts
 create mode 100644 arch/arm64/boot/dts/airoha/an7583.dtsi

diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
index ebea112ce1d7..7a604ae249b5 100644
--- a/arch/arm64/boot/dts/airoha/Makefile
+++ b/arch/arm64/boot/dts/airoha/Makefile
@@ -1,2 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0-only
 dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
+dtb-$(CONFIG_ARCH_AIROHA) += an7583-evb.dtb
diff --git a/arch/arm64/boot/dts/airoha/an7583-evb.dts b/arch/arm64/boot/dts/airoha/an7583-evb.dts
new file mode 100644
index 000000000000..a7f83436825e
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/an7583-evb.dts
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/dts-v1/;
+
+#include "an7583.dtsi"
+
+/ {
+	model = "Airoha EN7583 Evaluation Board";
+	compatible = "airoha,an7583-evb", "airoha,an7583";
+
+	aliases {
+		serial0 = &uart1;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x2 0x00000000>;
+	};
+};
diff --git a/arch/arm64/boot/dts/airoha/an7583.dtsi b/arch/arm64/boot/dts/airoha/an7583.dtsi
new file mode 100644
index 000000000000..a6a5df60d0e1
--- /dev/null
+++ b/arch/arm64/boot/dts/airoha/an7583.dtsi
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0>;
+			operating-points-v2 = <&cpu_opp_table>;
+			enable-method = "psci";
+			clocks = <&cpufreq>;
+			clock-names = "cpu";
+			power-domains = <&cpufreq>;
+			power-domain-names = "perf";
+			next-level-cache = <&l2>;
+			#cooling-cells = <2>;
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x1>;
+			operating-points-v2 = <&cpu_opp_table>;
+			enable-method = "psci";
+			clocks = <&cpufreq>;
+			clock-names = "cpu";
+			power-domains = <&cpufreq>;
+			power-domain-names = "perf";
+			next-level-cache = <&l2>;
+			#cooling-cells = <2>;
+		};
+
+		l2: l2-cache {
+			compatible = "cache";
+			cache-size = <0x80000>;
+			cache-line-size = <64>;
+			cache-level = <2>;
+			cache-unified;
+		};
+	};
+
+	cpufreq: cpufreq {
+		compatible = "airoha,en7581-cpufreq";
+
+		operating-points-v2 = <&smcc_opp_table>;
+
+		#power-domain-cells = <0>;
+		#clock-cells = <0>;
+	};
+
+	cpu_opp_table: opp-table-cpu {
+		compatible = "operating-points-v2";
+		opp-shared;
+
+		opp-500000000 {
+			opp-hz = /bits/ 64 <500000000>;
+			required-opps = <&smcc_opp0>;
+		};
+
+		opp-550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			required-opps = <&smcc_opp1>;
+		};
+
+		opp-600000000 {
+			opp-hz = /bits/ 64 <600000000>;
+			required-opps = <&smcc_opp2>;
+		};
+
+		opp-650000000 {
+			opp-hz = /bits/ 64 <650000000>;
+			required-opps = <&smcc_opp3>;
+		};
+
+		opp-7000000000 {
+			opp-hz = /bits/ 64 <700000000>;
+			required-opps = <&smcc_opp4>;
+		};
+
+		opp-7500000000 {
+			opp-hz = /bits/ 64 <750000000>;
+			required-opps = <&smcc_opp5>;
+		};
+
+		opp-8000000000 {
+			opp-hz = /bits/ 64 <800000000>;
+			required-opps = <&smcc_opp6>;
+		};
+
+		opp-8500000000 {
+			opp-hz = /bits/ 64 <850000000>;
+			required-opps = <&smcc_opp7>;
+		};
+
+		opp-9000000000 {
+			opp-hz = /bits/ 64 <900000000>;
+			required-opps = <&smcc_opp8>;
+		};
+
+		opp-9500000000 {
+			opp-hz = /bits/ 64 <950000000>;
+			required-opps = <&smcc_opp9>;
+		};
+
+		opp-10000000000 {
+			opp-hz = /bits/ 64 <1000000000>;
+			required-opps = <&smcc_opp10>;
+		};
+
+		opp-10500000000 {
+			opp-hz = /bits/ 64 <1050000000>;
+			required-opps = <&smcc_opp11>;
+		};
+
+		opp-11000000000 {
+			opp-hz = /bits/ 64 <1100000000>;
+			required-opps = <&smcc_opp12>;
+		};
+
+		opp-11500000000 {
+			opp-hz = /bits/ 64 <1150000000>;
+			required-opps = <&smcc_opp13>;
+		};
+
+		opp-12000000000 {
+			opp-hz = /bits/ 64 <1200000000>;
+			required-opps = <&smcc_opp14>;
+		};
+	};
+
+	smcc_opp_table: opp-table-smcc {
+		compatible = "operating-points-v2";
+
+		smcc_opp0: opp-0 {
+			opp-level = <0>;
+		};
+
+		smcc_opp1: opp-1 {
+			opp-level = <1>;
+		};
+
+		smcc_opp2: opp-2 {
+			opp-level = <2>;
+		};
+
+		smcc_opp3: opp-3 {
+			opp-level = <3>;
+		};
+
+		smcc_opp4: opp-4 {
+			opp-level = <4>;
+		};
+
+		smcc_opp5: opp-5 {
+			opp-level = <5>;
+		};
+
+		smcc_opp6: opp-6 {
+			opp-level = <6>;
+		};
+
+		smcc_opp7: opp-7 {
+			opp-level = <7>;
+		};
+
+		smcc_opp8: opp-8 {
+			opp-level = <8>;
+		};
+
+		smcc_opp9: opp-9 {
+			opp-level = <9>;
+		};
+
+		smcc_opp10: opp-10 {
+			opp-level = <10>;
+		};
+
+		smcc_opp11: opp-11 {
+			opp-level = <11>;
+		};
+
+		smcc_opp12: opp-12 {
+			opp-level = <12>;
+		};
+
+		smcc_opp13: opp-13 {
+			opp-level = <13>;
+		};
+
+		smcc_opp14: opp-14 {
+			opp-level = <14>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	sys_hclk: clk-oscillator-100mhz {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sys_hclk";
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@9000000 {
+			compatible = "arm,gic-v3";
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x0 0x09000000 0x0 0x20000>,
+			      <0x0 0x09080000 0x0 0x80000>,
+			      <0x0 0x09400000 0x0 0x2000>,
+			      <0x0 0x09500000 0x0 0x2000>,
+			      <0x0 0x09600000 0x0 0x20000>;
+			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+		};
+
+		crypto@1e004000 {
+			compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
+			reg = <0x0 0x1fb70000 0x0 0x1000>;
+
+			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		uart1: serial@1fbf0000 {
+			compatible = "ns16550";
+			reg = <0x0 0x1fbf0000 0x0 0x30>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <1843200>;
+		};
+
+		watchdog@1fbf0100 {
+			compatible = "airoha,en7581-wdt";
+			reg = <0x0 0x1fbf0100 0x0 0x38>;
+
+			clocks = <&sys_hclk>;
+			clock-names = "bus";
+		};
+	};
+};
-- 
2.51.0

Re: [PATCH v2 2/2] arm64: dts: Add Airoha AN7583 SoC and AN7583 Evaluation Board

[AngeloGioacchino Del Regno]

Il 23/09/25 20:53, Christian Marangi ha scritto:
> Introduce Airoha AN7583 SoC initial DTSI and AN7583 Evaluation Board
> DTS and add the required entry in the Makefile.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> Changes v2:
> - Fix DTB BOT warning (fix crypto compatible and OPP node name)
> 
>   arch/arm64/boot/dts/airoha/Makefile       |   1 +
>   arch/arm64/boot/dts/airoha/an7583-evb.dts |  22 ++
>   arch/arm64/boot/dts/airoha/an7583.dtsi    | 282 ++++++++++++++++++++++
>   3 files changed, 305 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/airoha/an7583-evb.dts
>   create mode 100644 arch/arm64/boot/dts/airoha/an7583.dtsi
> 
> diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile
> index ebea112ce1d7..7a604ae249b5 100644
> --- a/arch/arm64/boot/dts/airoha/Makefile
> +++ b/arch/arm64/boot/dts/airoha/Makefile
> @@ -1,2 +1,3 @@
>   # SPDX-License-Identifier: GPL-2.0-only
>   dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb
> +dtb-$(CONFIG_ARCH_AIROHA) += an7583-evb.dtb
> diff --git a/arch/arm64/boot/dts/airoha/an7583-evb.dts b/arch/arm64/boot/dts/airoha/an7583-evb.dts
> new file mode 100644
> index 000000000000..a7f83436825e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/an7583-evb.dts
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/dts-v1/;
> +
> +#include "an7583.dtsi"
> +
> +/ {
> +	model = "Airoha EN7583 Evaluation Board";

There's a typo - you wrote EN instead of AN.

> +	compatible = "airoha,an7583-evb", "airoha,an7583";
> +
> +	aliases {
> +		serial0 = &uart1;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial0:115200n8";
> +	};
> +
> +	memory@80000000 {
> +		device_type = "memory";
> +		reg = <0x0 0x80000000 0x2 0x00000000>;
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/airoha/an7583.dtsi b/arch/arm64/boot/dts/airoha/an7583.dtsi
> new file mode 100644
> index 000000000000..a6a5df60d0e1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/airoha/an7583.dtsi
> @@ -0,0 +1,282 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			enable-method = "psci";
> +			clocks = <&cpufreq>;
> +			clock-names = "cpu";
> +			power-domains = <&cpufreq>;
> +			power-domain-names = "perf";
> +			next-level-cache = <&l2>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x1>;
> +			operating-points-v2 = <&cpu_opp_table>;
> +			enable-method = "psci";
> +			clocks = <&cpufreq>;
> +			clock-names = "cpu";
> +			power-domains = <&cpufreq>;
> +			power-domain-names = "perf";
> +			next-level-cache = <&l2>;
> +			#cooling-cells = <2>;
> +		};
> +
> +		l2: l2-cache {
> +			compatible = "cache";
> +			cache-size = <0x80000>;
> +			cache-line-size = <64>;
> +			cache-level = <2>;
> +			cache-unified;
> +		};
> +	};
> +
> +	cpufreq: cpufreq {
> +		compatible = "airoha,en7581-cpufreq";
> +
> +		operating-points-v2 = <&smcc_opp_table>;
> +
> +		#power-domain-cells = <0>;
> +		#clock-cells = <0>;
> +	};
> +
> +	cpu_opp_table: opp-table-cpu {
> +		compatible = "operating-points-v2";
> +		opp-shared;
> +
> +		opp-500000000 {
> +			opp-hz = /bits/ 64 <500000000>;
> +			required-opps = <&smcc_opp0>;
> +		};
> +
> +		opp-550000000 {
> +			opp-hz = /bits/ 64 <550000000>;
> +			required-opps = <&smcc_opp1>;
> +		};
> +
> +		opp-600000000 {
> +			opp-hz = /bits/ 64 <600000000>;
> +			required-opps = <&smcc_opp2>;
> +		};
> +
> +		opp-650000000 {
> +			opp-hz = /bits/ 64 <650000000>;
> +			required-opps = <&smcc_opp3>;
> +		};
> +
> +		opp-7000000000 {
> +			opp-hz = /bits/ 64 <700000000>;
> +			required-opps = <&smcc_opp4>;
> +		};
> +
> +		opp-7500000000 {
> +			opp-hz = /bits/ 64 <750000000>;
> +			required-opps = <&smcc_opp5>;
> +		};
> +
> +		opp-8000000000 {
> +			opp-hz = /bits/ 64 <800000000>;
> +			required-opps = <&smcc_opp6>;
> +		};
> +
> +		opp-8500000000 {
> +			opp-hz = /bits/ 64 <850000000>;
> +			required-opps = <&smcc_opp7>;
> +		};
> +
> +		opp-9000000000 {
> +			opp-hz = /bits/ 64 <900000000>;
> +			required-opps = <&smcc_opp8>;
> +		};
> +
> +		opp-9500000000 {
> +			opp-hz = /bits/ 64 <950000000>;
> +			required-opps = <&smcc_opp9>;
> +		};
> +
> +		opp-10000000000 {
> +			opp-hz = /bits/ 64 <1000000000>;
> +			required-opps = <&smcc_opp10>;
> +		};
> +
> +		opp-10500000000 {
> +			opp-hz = /bits/ 64 <1050000000>;
> +			required-opps = <&smcc_opp11>;
> +		};
> +
> +		opp-11000000000 {
> +			opp-hz = /bits/ 64 <1100000000>;
> +			required-opps = <&smcc_opp12>;
> +		};
> +
> +		opp-11500000000 {
> +			opp-hz = /bits/ 64 <1150000000>;
> +			required-opps = <&smcc_opp13>;
> +		};
> +
> +		opp-12000000000 {
> +			opp-hz = /bits/ 64 <1200000000>;
> +			required-opps = <&smcc_opp14>;
> +		};
> +	};
> +
> +	smcc_opp_table: opp-table-smcc {
> +		compatible = "operating-points-v2";
> +
> +		smcc_opp0: opp-0 {
> +			opp-level = <0>;
> +		};
> +
> +		smcc_opp1: opp-1 {
> +			opp-level = <1>;
> +		};
> +
> +		smcc_opp2: opp-2 {
> +			opp-level = <2>;
> +		};
> +
> +		smcc_opp3: opp-3 {
> +			opp-level = <3>;
> +		};
> +
> +		smcc_opp4: opp-4 {
> +			opp-level = <4>;
> +		};
> +
> +		smcc_opp5: opp-5 {
> +			opp-level = <5>;
> +		};
> +
> +		smcc_opp6: opp-6 {
> +			opp-level = <6>;
> +		};
> +
> +		smcc_opp7: opp-7 {
> +			opp-level = <7>;
> +		};
> +
> +		smcc_opp8: opp-8 {
> +			opp-level = <8>;
> +		};
> +
> +		smcc_opp9: opp-9 {
> +			opp-level = <9>;
> +		};
> +
> +		smcc_opp10: opp-10 {
> +			opp-level = <10>;
> +		};
> +
> +		smcc_opp11: opp-11 {
> +			opp-level = <11>;
> +		};
> +
> +		smcc_opp12: opp-12 {
> +			opp-level = <12>;
> +		};
> +
> +		smcc_opp13: opp-13 {
> +			opp-level = <13>;
> +		};
> +
> +		smcc_opp14: opp-14 {
> +			opp-level = <14>;
> +		};
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupt-parent = <&gic>;
> +		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
> +			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	sys_hclk: clk-oscillator-100mhz {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +		clock-output-names = "sys_hclk";
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		gic: interrupt-controller@9000000 {
> +			compatible = "arm,gic-v3";
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			reg = <0x0 0x09000000 0x0 0x20000>,
> +			      <0x0 0x09080000 0x0 0x80000>,
> +			      <0x0 0x09400000 0x0 0x2000>,
> +			      <0x0 0x09500000 0x0 0x2000>,
> +			      <0x0 0x09600000 0x0 0x20000>;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
> +		};
> +
> +		crypto@1e004000 {
> +			compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";

First of all: sorry for not catching this in the first review.

This is wrong - the compatible string must contain the SoC compatible, but this is
AN7583, not EN7581.

Either of

compatible = "airoha,an7583-eip93", "inside-secure,safexcel-eip93ies";

or

compatible = "airoha,an7583-eip93", "airoha,en7581-eip93",
	     "inside-secure,safexcel-eip93ies";

is acceptable. Of course, you have to add that to the bindings.

> +			reg = <0x0 0x1fb70000 0x0 0x1000>;
> +
> +			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		uart1: serial@1fbf0000 {
> +			compatible = "ns16550";
> +			reg = <0x0 0x1fbf0000 0x0 0x30>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
> +			clock-frequency = <1843200>;
> +		};
> +
> +		watchdog@1fbf0100 {
> +			compatible = "airoha,en7581-wdt";

compatible = "airoha,an7583-wdt", "airoha,en7581-wdt";

(and add to the bindings)

Everything else looks ok.

Cheers,
Angelo

Re: [PATCH v2 1/2] dt-bindings: arm64: dts: airoha: Add AN7583 compatible

[AngeloGioacchino Del Regno]

Il 23/09/25 20:53, Christian Marangi ha scritto:
> Add Airoha AN7583 compatible to the list of enum for Airoha Supported
> SoCs.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Re: [PATCH v2 1/2] dt-bindings: arm64: dts: airoha: Add AN7583 compatible

[Rob Herring (Arm)]

On Tue, 23 Sep 2025 20:53:34 +0200, Christian Marangi wrote:
> Add Airoha AN7583 compatible to the list of enum for Airoha Supported
> SoCs.
> 
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> ---
> Changes v2:
> - Follow alphabetical order
> 
>  Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++
>  1 file changed, 4 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>