From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D54BDCAC5B5 for ; Thu, 25 Sep 2025 21:58:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=uqTQx9LUkIe0/ub4yjVNAA6+owlalcgdNtwtnIvFdxE=; b=a5475XHmZXm7bb cpzPJRS9hRPZTUUBA7wwC2t65Am4KUyT5FVODrkElWgcPJPz83Bb+fdlg965mgFv9zTDEdqD1nyzP LPHplKsTJRb6cmY31Hs98I9lsC7L4IuoITqBZCWW1HP3t8yp7c6DbXp4+LcDOEaep3dDXuhfdQTuy Rca1+Smtmbn1pzRlujo+mMpE+1Y4ScT/6Km4VnB0+2vknLFKCNNE8vUfmDj8V6zc69TXR+BL0Tr7B lKDAFIJm2+q67NTnjgjC1bN+V+AXJExtdttpBTstHDZ9kNFAE07beFrk7PSf5mruI3v6EGrbN7GZV 5x9zEn9xQRxSsXrkMwlQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v1tyT-0000000DNV3-3gjk; Thu, 25 Sep 2025 21:58:01 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v1tyR-0000000DNUx-3IU6 for linux-arm-kernel@lists.infradead.org; Thu, 25 Sep 2025 21:57:59 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 27F6E61282; Thu, 25 Sep 2025 21:57:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AAA3EC4CEF0; Thu, 25 Sep 2025 21:57:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758837478; bh=XSHViZo3Pi55CeXnpkwa+76DxWBGmZaI9vptrJBuf3Y=; h=Date:From:To:Cc:Subject:In-Reply-To:From; b=O9jw1uPIi82h87JIKbVTIqu+AZDAM6k59eR34EetiOXMbG80a0szGPh5gViG08yGl /QUNaZ27F2FodFn/W1wqFbHSTGFO+dbS9UK1VEVHUI+BOYgO2wr1LrUSvIiwx54EFj cC+Ynvw9g8wd/RcH0Lki2jVBgwo4GQrA+OPJWkK+gAokG3V9doBxAQ33aIz9teJGqx T6ow1SftLrX7eYgxfMNiRvsdTzW2miiSy0qxTChgG4uzufaUT1Ggrb3a/wVsa9kXg2 MQEDzbZm4IlpLxs8hQ+Xm7FZhfoQ4HPZGXSHRve9tmG1jLdMjHGj8PfS5dXyYWU/sO saYoyggiS0edA== Date: Thu, 25 Sep 2025 16:57:57 -0500 From: Bjorn Helgaas To: Richard Zhu Cc: frank.li@nxp.com, jingoohan1@gmail.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 2/2] PCI: imx6: Add a method to handle CLKREQ# override active low Message-ID: <20250925215757.GA2205491@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250923073913.2722668-3-hongxing.zhu@nxp.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Sep 23, 2025 at 03:39:13PM +0800, Richard Zhu wrote: > The CLKREQ# is an open drain, active low signal that is driven low by > the card to request reference clock. It's an optional signal added in > PCIe CEM r4.0, sec 2. Thus, this signal wouldn't be driven low if it's > reserved. > > Since the reference clock controlled by CLKREQ# may be required by i.MX > PCIe host too. To make sure this clock is ready even when the CLKREQ# > isn't driven low by the card(e.x the scenario described above), force > CLKREQ# override active low for i.MX PCIe host during initialization. > > The CLKREQ# override can be cleared safely when supports-clkreq is > present and PCIe link is up later. Because the CLKREQ# would be driven > low by the card at this time. > > Signed-off-by: Richard Zhu > Reviewed-by: Frank Li > --- > drivers/pci/controller/dwc/pci-imx6.c | 43 ++++++++++++++++++++++++++- > 1 file changed, 42 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 80e48746bbaf..6b03b1111d06 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -52,6 +52,8 @@ > #define IMX95_PCIE_REF_CLKEN BIT(23) > #define IMX95_PCIE_PHY_CR_PARA_SEL BIT(9) > #define IMX95_PCIE_SS_RW_REG_1 0xf4 > +#define IMX95_PCIE_CLKREQ_OVERRIDE_EN BIT(8) > +#define IMX95_PCIE_CLKREQ_OVERRIDE_VAL BIT(9) > #define IMX95_PCIE_SYS_AUX_PWR_DET BIT(31) > > #define IMX95_PE0_GEN_CTRL_1 0x1050 > @@ -136,6 +138,7 @@ struct imx_pcie_drvdata { > int (*enable_ref_clk)(struct imx_pcie *pcie, bool enable); > int (*core_reset)(struct imx_pcie *pcie, bool assert); > int (*wait_pll_lock)(struct imx_pcie *pcie); > + void (*clr_clkreq_override)(struct imx_pcie *pcie); > const struct dw_pcie_host_ops *ops; > }; > > @@ -149,6 +152,7 @@ struct imx_pcie { > struct gpio_desc *reset_gpiod; > struct clk_bulk_data *clks; > int num_clks; > + bool supports_clkreq; > struct regmap *iomuxc_gpr; > u16 msi_ctrl; > u32 controller_id; > @@ -239,6 +243,16 @@ static unsigned int imx_pcie_grp_offset(const struct imx_pcie *imx_pcie) > return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; > } > > +static void imx95_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable) > +{ > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1, > + IMX95_PCIE_CLKREQ_OVERRIDE_EN, > + enable ? IMX95_PCIE_CLKREQ_OVERRIDE_EN : 0); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_SS_RW_REG_1, > + IMX95_PCIE_CLKREQ_OVERRIDE_VAL, > + enable ? IMX95_PCIE_CLKREQ_OVERRIDE_VAL : 0); > +} > + > static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) > { > /* > @@ -685,7 +699,7 @@ static int imx6q_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) > return 0; > } > > -static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +static void imx8mm_pcie_clkreq_override(struct imx_pcie *imx_pcie, bool enable) > { > int offset = imx_pcie_grp_offset(imx_pcie); > > @@ -695,6 +709,11 @@ static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) > regmap_update_bits(imx_pcie->iomuxc_gpr, offset, > IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN, > enable ? IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN : 0); > +} > + > +static int imx8mm_pcie_enable_ref_clk(struct imx_pcie *imx_pcie, bool enable) > +{ > + imx8mm_pcie_clkreq_override(imx_pcie, enable); > return 0; > } > > @@ -1298,6 +1317,16 @@ static void imx_pcie_host_exit(struct dw_pcie_rp *pp) > regulator_disable(imx_pcie->vpcie); > } > > +static void imx8mm_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie) > +{ > + imx8mm_pcie_clkreq_override(imx_pcie, false); > +} > + > +static void imx95_pcie_clr_clkreq_override(struct imx_pcie *imx_pcie) > +{ > + imx95_pcie_clkreq_override(imx_pcie, false); > +} > + > static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > @@ -1322,6 +1351,12 @@ static void imx_pcie_host_post_init(struct dw_pcie_rp *pp) > dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val); > dw_pcie_dbi_ro_wr_dis(pci); > } > + > + /* Clear CLKREQ# override if supports_clkreq is true and link is up */ > + if (dw_pcie_link_up(pci) && imx_pcie->supports_clkreq) { > + if (imx_pcie->drvdata->clr_clkreq_override) > + imx_pcie->drvdata->clr_clkreq_override(imx_pcie); > + } > } > > /* > @@ -1745,6 +1780,8 @@ static int imx_pcie_probe(struct platform_device *pdev) > pci->max_link_speed = 1; > of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed); > > + imx_pcie->supports_clkreq = > + of_property_read_bool(node, "supports-clkreq"); > imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); > if (IS_ERR(imx_pcie->vpcie)) { > if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) > @@ -1873,6 +1910,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_mask[1] = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE, > .init_phy = imx8mq_pcie_init_phy, > .enable_ref_clk = imx8mm_pcie_enable_ref_clk, > + .clr_clkreq_override = imx8mm_pcie_clr_clkreq_override, > }, > [IMX8MM] = { > .variant = IMX8MM, > @@ -1883,6 +1921,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_off[0] = IOMUXC_GPR12, > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .enable_ref_clk = imx8mm_pcie_enable_ref_clk, > + .clr_clkreq_override = imx8mm_pcie_clr_clkreq_override, > }, > [IMX8MP] = { > .variant = IMX8MP, > @@ -1893,6 +1932,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .mode_off[0] = IOMUXC_GPR12, > .mode_mask[0] = IMX6Q_GPR12_DEVICE_TYPE, > .enable_ref_clk = imx8mm_pcie_enable_ref_clk, > + .clr_clkreq_override = imx8mm_pcie_clr_clkreq_override, imx8mm_pcie_enable_ref_clk() and imx8mm_pcie_clr_clkreq_override() both call imx8mm_pcie_clkreq_override(). All these devices that use imx8mm_pcie_clr_clkreq_override() also enable the refclk in .init() by overriding clkreq, so .post_init() clears that override. > }, > [IMX8Q] = { > .variant = IMX8Q, > @@ -1913,6 +1953,7 @@ static const struct imx_pcie_drvdata drvdata[] = { > .core_reset = imx95_pcie_core_reset, > .init_phy = imx95_pcie_init_phy, > .wait_pll_lock = imx95_pcie_wait_for_phy_pll_lock, > + .clr_clkreq_override = imx95_pcie_clr_clkreq_override, But here there's no .enable_ref_clk() method, so I guess this device must override clkreq automatically and the driver doesn't have to enable that? > }, > [IMX8MQ_EP] = { > .variant = IMX8MQ_EP, > -- > 2.37.1 >