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charset=us-ascii Content-Disposition: inline In-Reply-To: <20250925162332.9794-5-ansuelsmth@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250926_143207_505071_37DC08CD X-CRM114-Status: GOOD ( 27.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Sep 25, 2025 at 06:23:18PM +0200, Christian Marangi wrote: > Add support for the second PCIe line present on Airoha AN7583 SoC. > > This is based on the Mediatek Gen1/2 PCIe driver and similar to Gen3 > also require workaround for the reset signals. > > Introduce a new bool to skip having to reset signals and also introduce > some additional logic to configure the PBUS registers required for > Airoha SoC. > > Signed-off-by: Christian Marangi > --- > drivers/pci/controller/pcie-mediatek.c | 85 +++++++++++++++++++------- > 1 file changed, 63 insertions(+), 22 deletions(-) > > diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c > index 24cc30a2ab6c..640d1f1a6478 100644 > --- a/drivers/pci/controller/pcie-mediatek.c > +++ b/drivers/pci/controller/pcie-mediatek.c > @@ -147,6 +147,7 @@ struct mtk_pcie_port; > * @need_fix_class_id: whether this host's class ID needed to be fixed or not > * @need_fix_device_id: whether this host's device ID needed to be fixed or not > * @no_msi: Bridge has no MSI support, and relies on an external block > + * @skip_pcie_rstb: Skip calling RSTB bits on PCIe probe > * @device_id: device ID which this host need to be fixed > * @ops: pointer to configuration access functions > * @startup: pointer to controller setting functions > @@ -156,6 +157,7 @@ struct mtk_pcie_soc { > bool need_fix_class_id; > bool need_fix_device_id; > bool no_msi; > + bool skip_pcie_rstb; > unsigned int device_id; > struct pci_ops *ops; > int (*startup)(struct mtk_pcie_port *port); > @@ -679,28 +681,30 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port) > regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val); > } > > - /* Assert all reset signals */ > - writel(0, port->base + PCIE_RST_CTRL); > - > - /* > - * Enable PCIe link down reset, if link status changed from link up to > - * link down, this will reset MAC control registers and configuration > - * space. > - */ > - writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > - > - /* > - * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > - * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > - * be delayed 100ms (TPVPERL) for the power and clock to become stable. > - */ > - msleep(100); > - > - /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > - val = readl(port->base + PCIE_RST_CTRL); > - val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > - PCIE_MAC_SRSTB | PCIE_CRSTB; > - writel(val, port->base + PCIE_RST_CTRL); > + if (!soc->skip_pcie_rstb) { > + /* Assert all reset signals */ > + writel(0, port->base + PCIE_RST_CTRL); > + > + /* > + * Enable PCIe link down reset, if link status changed from link up to > + * link down, this will reset MAC control registers and configuration > + * space. > + */ > + writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL); > + > + /* > + * Described in PCIe CEM specification sections 2.2 (PERST# Signal) and > + * 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should > + * be delayed 100ms (TPVPERL) for the power and clock to become stable. > + */ > + msleep(100); > + > + /* De-assert PHY, PE, PIPE, MAC and configuration reset */ > + val = readl(port->base + PCIE_RST_CTRL); > + val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB | > + PCIE_MAC_SRSTB | PCIE_CRSTB; > + writel(val, port->base + PCIE_RST_CTRL); > + } > > /* Set up vendor ID and class code */ > if (soc->need_fix_class_id) { > @@ -1105,6 +1109,33 @@ static int mtk_pcie_probe(struct platform_device *pdev) > if (err) > goto put_resources; > > + if (device_is_compatible(dev, "airoha,an7583-pcie")) { This should check some match data flag rather than checking compatible again. Otherwise this becomes device_is_compatible() || device_is_compatible() || device_is_compatible()... Rob