Re: [PATCH 1/3] dt-bindings: spi: spi-cadence: document optional fifo-width DT property

[Conor Dooley <conor@kernel.org>]

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On Tue, Sep 30, 2025 at 03:56:42PM +0800, Jun Guo wrote:
> Add documentation for the optional 'fifo-width' device tree property
> for the Cadence SPI controller.
> 
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> ---
>  .../devicetree/bindings/spi/spi-cadence.yaml          | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/spi/spi-cadence.yaml b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> index 8de96abe9da1..b2e3f217473b 100644
> --- a/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> +++ b/Documentation/devicetree/bindings/spi/spi-cadence.yaml
> @@ -62,6 +62,17 @@ properties:
>      items:
>        - const: spi
>  
> +  fifo-width:
> +    description: |
> +      This property specifies the FIFO data width (in bits) of the hardware.
> +      It must be configured according to the actual FIFO width set during
> +      the IP design. For instance, if the hardware FIFO is 32 bits wide,
> +      this property should be set to 32.
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    minimum: 8
> +    maximum: 32
> +    default: 8

I assume this differs from fifo-depth because this is the actual width
of the registers rather than the number of elements of that width the
FIFO can contain?

However, this isn't something defined as common in spi-controller.yaml
so you'll need a vendor prefix for the property if the property stays.
This does, however, seem like something that can just be determined by
the compatible and that your omission of a soc-specific one is what's
lead you to introduce this property. Why not just use a sky1-specific
compatible here?

> +
>  required:
>    - compatible
>    - reg
> -- 
> 2.34.1
> 

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