From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FFCBCAC5B0 for ; Fri, 3 Oct 2025 20:16:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MyTZIankaLF5a06YDy1KIdFXkQpVaw5MiopvoWPWCGU=; b=Fw0ySlCc087zIg7qEY/OWRYCgx sptE9G2v03sii14ghhlps0PtUTT47zwb9RqusQMg1mT3iVaAJIp8wLo3QCB+m+EceBgvMWgEIkEKL aXkGF4+ddl9ltK2rGA8IgGlwmfFSgmlQB56h1qpfD8byz9c8HixiogiNhyEgUutdZmrL3t0ASU8XB 7PHYFEN2a90Y+Jgm7VkYoYAbG+AJJ7Nfbwpfwdgo++ESFauaD4lSLdbvEtzr75PCvJtPqSbRsZKzl t+ZiKXiHyR/LH8xoWQEm/k7FFP44K2ONkzkcKeIS3lffpMlX8ro0E1GPdmPmXBcRjzMRYshkmenmU pmBQu6XQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v4mCU-0000000D3dU-0NfX; Fri, 03 Oct 2025 20:16:22 +0000 Received: from sender4-pp-f112.zoho.com ([136.143.188.112]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v4mCR-0000000D3aI-363m; Fri, 03 Oct 2025 20:16:20 +0000 ARC-Seal: i=1; a=rsa-sha256; t=1759522541; cv=none; d=zohomail.com; s=zohoarc; b=EGsR7BrvMlzQiGzSUqbjkdcpwEhwClVLQUTL1hBcvpeHooPOYWyteFVMUQy7gMAxgR6pgD9cUKE/seb/k96UUrMbP1sRgBMaBRv0MUGbdI9RYNPC5fqtKvFIJ9QGRovR0JmVGe/NwSek+nqra/uumVBn4psyWqZP999MTNzy518= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1759522541; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=MyTZIankaLF5a06YDy1KIdFXkQpVaw5MiopvoWPWCGU=; b=ToaYnCMsM4BUh7jGSRQ8/8t75GqCeAQ/T7mQkb5xeWgG82lfhuaS2dzueN2F7a5/XS6lBYIOWrhHoukEfuiGI7BcJVbZYpNiASdjclObl4QOtUGpKNzK9u+1awn/GLdUHAZizTnZfonEI9RjUlUqNPRKQHFv3aq1I2bLPIdJ2Qw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1759522541; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=MyTZIankaLF5a06YDy1KIdFXkQpVaw5MiopvoWPWCGU=; b=F3vppZbGfNEvnAj1nGUnzqTzc6d/RQ1wfXBA7LqXa42YxPWpj2GrjraNhfqCZGBw FLgN9bMYm+JYnAQXmr9glUB6wM2Qi8IC0YVS8uOQSh8rLaYDfnoz6qsKoloN1Z45K7v xTO58NJyA6YLK5A38oz0WodX4hCt86YREa8KBUDI= Received: by mx.zohomail.com with SMTPS id 1759522534788242.36207723608516; Fri, 3 Oct 2025 13:15:34 -0700 (PDT) From: Nicolas Frattaroli Date: Fri, 03 Oct 2025 22:15:03 +0200 Subject: [PATCH v6 1/7] dt-bindings: gpu: mali-valhall-csf: add mediatek,mt8196-mali variant MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251003-mt8196-gpufreq-v6-1-76498ad61d9e@collabora.com> References: <20251003-mt8196-gpufreq-v6-0-76498ad61d9e@collabora.com> In-Reply-To: <20251003-mt8196-gpufreq-v6-0-76498ad61d9e@collabora.com> To: AngeloGioacchino Del Regno , Boris Brezillon , Jassi Brar , Chia-I Wu , Chen-Yu Tsai , Steven Price , Liviu Dudau , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , Kees Cook , "Gustavo A. R. Silva" , Ulf Hansson Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-hardening@vger.kernel.org, linux-pm@vger.kernel.org, Nicolas Frattaroli X-Mailer: b4 0.14.2 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251003_131619_845043_AF6FCD2E X-CRM114-Status: GOOD ( 11.35 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Mali-based GPU on the MediaTek MT8196 SoC uses a separate MCU to control the power and frequency of the GPU. This is modelled as a power domain and clock provider. It lets us omit the OPP tables from the device tree, as those can now be enumerated at runtime from the MCU. Add the necessary schema logic to handle what this SoC expects in terms of clocks and power-domains. Signed-off-by: Nicolas Frattaroli --- .../bindings/gpu/arm,mali-valhall-csf.yaml | 40 ++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml index 7ad5a3ffc5f5c753322eda9e74cc65de89d11c73..860691ce985e560536b6c515b82441ba6d367c46 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml @@ -45,7 +45,9 @@ properties: minItems: 1 items: - const: core - - const: coregroup + - enum: + - coregroup + - stacks - const: stacks mali-supply: true @@ -92,7 +94,6 @@ required: - interrupts - interrupt-names - clocks - - mali-supply additionalProperties: false @@ -109,6 +110,29 @@ allOf: power-domains: maxItems: 1 power-domain-names: false + required: + - mali-supply + - if: + properties: + compatible: + contains: + const: mediatek,mt8196-mali + then: + properties: + mali-supply: false + sram-supply: false + operating-points-v2: false + power-domains: + maxItems: 1 + power-domain-names: false + clocks: + maxItems: 2 + clock-names: + items: + - const: core + - const: stacks + required: + - power-domains examples: - | @@ -144,5 +168,17 @@ examples: }; }; }; + - | + gpu@48000000 { + compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf"; + reg = <0x48000000 0x480000>; + clocks = <&gpufreq 0>, <&gpufreq 1>; + clock-names = "core", "stacks"; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + power-domains = <&gpufreq>; + }; ... -- 2.51.0