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Tue, 07 Oct 2025 23:00:13 -0700 (PDT) Date: Wed, 8 Oct 2025 05:59:57 +0000 In-Reply-To: <20251008060000.3136021-1-royluo@google.com> Mime-Version: 1.0 References: <20251008060000.3136021-1-royluo@google.com> X-Mailer: git-send-email 2.51.0.710.ga91ca5db03-goog Message-ID: <20251008060000.3136021-2-royluo@google.com> Subject: [PATCH v2 1/4] dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 From: Roy Luo To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Greg Kroah-Hartman , Thinh Nguyen , Philipp Zabel , Peter Griffin , "=?UTF-8?q?Andr=C3=A9=20Draszik?=" , Tudor Ambarus Cc: Joy Chakraborty , Naveen Kumar , Roy Luo , Badhri Jagan Sridharan , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251007_230014_322275_489862F2 X-CRM114-Status: GOOD ( 16.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document the device tree bindings for the DWC3 USB controller found in Google Tensor SoCs, starting with the G5 generation. The Tensor G5 silicon represents a complete architectural departure from previous generations (like gs101), including entirely new clock/reset schemes, top-level wrapper and register interface. Consequently, existing Samsung/Exynos DWC3 USB bindings and drivers are incompatible, necessitating this new device tree binding. The USB controller on Tensor G5 is based on Synopsys DWC3 IP and features Dual-Role Device single port with hibernation support. Signed-off-by: Roy Luo --- .../bindings/usb/google,gs-dwc3.yaml | 145 ++++++++++++++++++ 1 file changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml diff --git a/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml new file mode 100644 index 000000000000..9eb0bf726e8d --- /dev/null +++ b/Documentation/devicetree/bindings/usb/google,gs-dwc3.yaml @@ -0,0 +1,145 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright (c) 2025, Google LLC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/google,gs-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Google Tensor Series (G5+) DWC3 USB SoC Controller + +maintainers: + - Roy Luo + +description: | + Describes the DWC3 USB controller block implemented on Google Tensor SoCs, + starting with the G5 generation. Based on Synopsys DWC3 IP, the controller + features Dual-Role Device single port with hibernation add-on. + +properties: + compatible: + items: + - enum: + - google,gs5-dwc3 + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + description: | + The following memory regions must present: + - dwc3_core: Core DWC3 IP registers. + - host_cfg_csr: Hibernation control registers. + - usbint_csr: Hibernation interrupt registers. + items: + - const: dwc3_core + - const: host_cfg_csr + - const: usbint_csr + + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + description: | + The following interrupts must present: + - dwc_usb3: Core DWC3 interrupt. + - hs_pme_irq: High speed remote wakeup interrupt for hibernation. + - ss_pme_irq: Super speed remote wakeup interrupt for hibernation. + items: + - const: dwc_usb3 + - const: hs_pme_irq + - const: ss_pme_irq + + clocks: + minItems: 3 + maxItems: 3 + + clock-names: + minItems: 3 + maxItems: 3 + + resets: + minItems: 5 + maxItems: 5 + + reset-names: + items: + - const: usbc_non_sticky + - const: usbc_sticky + - const: usb_drd_bus + - const: u2phy_apb + - const: usb_top_csr + + power-domains: + minItems: 2 + maxItems: 2 + + power-domain-names: + description: | + The following power domain must present: + - usb_psw_pd: The child power domain of usb_top_pd. Turning it on puts the controller + into full power state, turning it off puts the controller into power + gated state. + - usb_top_pd: The parent power domain of usb_psw_pd. Turning it on puts the controller + into power gated state, turning it off completely shuts off the + controller. + items: + - const: usb_psw_pd + - const: usb_top_pd + + iommus: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - clocks + - resets + - reset-names + - power-domains + - power-domain-names + +allOf: + - $ref: snps,dwc3-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + usb@c400000 { + compatible = "google,gs5-dwc3"; + reg = <0 0x0c400000 0 0xd060>, <0 0x0c450000 0 0x14>, <0 0x0c450020 0 0x8>; + reg-names = "dwc3_core", "host_cfg_csr", "usbint_csr"; + interrupts = , + , + ; + interrupt-names = "dwc_usb3", "hs_pme_irq", "ss_pme_irq"; + clocks = <&hsion_usbc_non_sticky_clk>, <&hsion_usbc_sticky_clk>, + <&hsion_u2phy_apb_clk>; + clock-names = "usbc_non_sticky", "usbc_sticky", "u2phy_apb"; + resets = <&hsion_resets_usbc_non_sticky>, <&hsion_resets_usbc_sticky>, + <&hsion_resets_usb_drd_bus>, <&hsion_resets_u2phy_apb>, + <&hsion_resets_usb_top_csr>; + reset-names = "usbc_non_sticky", "usbc_sticky", + "usb_drd_bus", "u2phy_apb", + "usb_top_csr"; + power-domains = <&hsio_n_usb_psw_pd>, <&hsio_n_usb_pd>; + power-domain-names = "usb_psw_pd", "usb_top_pd"; + phys = <&usb_phy 0>; + phy-names = "usb2-phy"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,gfladj-refclk-lpm-sel-quirk; + snps,incr-burst-type-adjustment = <4>; + }; + }; +... -- 2.51.0.710.ga91ca5db03-goog