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Fri, 10 Oct 2025 15:48:16 +0000 (UTC) Received: from vschneid-thinkpadt14sgen2i.remote.csb (unknown [10.45.224.29]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id F0D471800578; Fri, 10 Oct 2025 15:48:01 +0000 (UTC) From: Valentin Schneider To: linux-kernel@vger.kernel.org, linux-mm@kvack.org, rcu@vger.kernel.org, x86@kernel.org, linux-arm-kernel@lists.infradead.org, loongarch@lists.linux.dev, linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-trace-kernel@vger.kernel.org Cc: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Andy Lutomirski , Peter Zijlstra , Arnaldo Carvalho de Melo , Josh Poimboeuf , Paolo Bonzini , Arnd Bergmann , Frederic Weisbecker , "Paul E. McKenney" , Jason Baron , Steven Rostedt , Ard Biesheuvel , Sami Tolvanen , "David S. Miller" , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , Boqun Feng , Uladzislau Rezki , Mathieu Desnoyers , Mel Gorman , Andrew Morton , Masahiro Yamada , Han Shen , Rik van Riel , Jann Horn , Dan Carpenter , Oleg Nesterov , Juri Lelli , Clark Williams , Yair Podemsky , Marcelo Tosatti , Daniel Wagner , Petr Tesarik Subject: [RFC PATCH v6 29/29] x86/entry: Add an option to coalesce TLB flushes Date: Fri, 10 Oct 2025 17:38:39 +0200 Message-ID: <20251010153839.151763-30-vschneid@redhat.com> In-Reply-To: <20251010153839.151763-1-vschneid@redhat.com> References: <20251010153839.151763-1-vschneid@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251010_164826_960409_EADE673D X-CRM114-Status: GOOD ( 18.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Previous patches have introduced a mechanism to prevent kernel text updates from inducing interference on isolated CPUs. A similar action is required for kernel-range TLB flushes in order to silence the biggest remaining cause of isolated CPU IPI interference. These flushes are mostly caused by vmalloc manipulations - e.g. on x86 with CONFIG_VMAP_STACK, spawning enough processes will easily trigger flushes. Unfortunately, the newly added context_tracking IPI deferral mechanism cannot be leveraged for TLB flushes, as the deferred work would be executed too late. Consider the following execution flow: !interrupt! SWITCH_TO_KERNEL_CR3 // vmalloc range becomes accessible idtentry_func_foo() irqentry_enter() irqentry_enter_from_user_mode() enter_from_user_mode() [...] ct_kernel_enter_state() ct_work_flush() // deferred flush would be done here Since there is no sane way to assert no stale entry is accessed during kernel entry, any code executed between SWITCH_TO_KERNEL_CR3 and ct_work_flush() is at risk of accessing a stale entry. Dave had suggested hacking up something within SWITCH_TO_KERNEL_CR3 itself, which is what has been implemented in the previous patches. Make kernel-range TLB flush deferral available via CONFIG_COALESCE_TLBI. Signed-off-by: Valentin Schneider --- arch/x86/Kconfig | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 3f1557b7acd8f..390e1dbe5d4de 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2188,6 +2188,23 @@ config ADDRESS_MASKING The capability can be used for efficient address sanitizers (ASAN) implementation and for optimizations in JITs. +config COALESCE_TLBI + def_bool n + prompt "Coalesce kernel TLB flushes for NOHZ-full CPUs" + depends on X86_64 && MITIGATION_PAGE_TABLE_ISOLATION && NO_HZ_FULL + help + TLB flushes for kernel addresses can lead to IPIs being sent to + NOHZ-full CPUs, thus kicking them out of userspace. + + This option coalesces kernel-range TLB flushes for NOHZ-full CPUs into + a single flush executed at kernel entry, right after switching to the + kernel page table. Note that this flush is unconditionnal, even if no + remote flush was issued during the previous userspace execution window. + + This obviously makes the user->kernel transition overhead even worse. + + If unsure, say N. + config HOTPLUG_CPU def_bool y depends on SMP -- 2.51.0