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bh=dyc2DoIYaPc0vTjiNx7YZ35hhTWb8Cwi1ST6UUpWQQ8=; b=TrzvXrQ6j6WQ/LeT2j/oRvx7muyGBT8qXa/My+2y8GIF6HLktL3rpy10QR7I5l4II8T0c6 M7Qkluxxi096YETNn1F36Teq7MOuj0feJfjth3wK42hrg7D2Q/rUnzD3nHx+5tXuW/D+kF kGV9+pYXegb41lgCF7Tex8z3EE2SCDy1Cdsn8NDt0kJvnTxQ7yDGcdfXh1RvqETXuJCI7m LpHkXIU9CFbkYFf7SBnrIGqnYJ+TgFYPAAUcIhMfyCECq7reouvXvFc08z4zt8zGo5zWsP wHCZYbh8exVJxpvd1sWyxcaUpeF09QDrB5kiXwnQdiLUh7aaG3mLV+wHgM2qVA== To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Laurent Pinchart , Liu Ying , Lucas Stach , Peng Fan , Pengutronix Kernel Team , Rob Herring , Shawn Guo , Thomas Zimmermann , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 25/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel interleaver support Date: Sat, 11 Oct 2025 18:51:40 +0200 Message-ID: <20251011170213.128907-26-marek.vasut@mailbox.org> In-Reply-To: <20251011170213.128907-1-marek.vasut@mailbox.org> References: <20251011170213.128907-1-marek.vasut@mailbox.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MBO-RS-ID: cb9dfd7a07ea323ab6e X-MBO-RS-META: ymqmomf8xzn1fjnaxof47mw1kfe48wyz X-Rspamd-Queue-Id: 4ckVM75VPfz9shj X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251011_101722_794532_BEA90812 X-CRM114-Status: GOOD ( 11.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document NXP i.MX95 pixel interleaver bridge support. Signed-off-by: Marek Vasut --- Cc: Abel Vesa Cc: Conor Dooley Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Laurent Pinchart Cc: Liu Ying Cc: Lucas Stach Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rob Herring Cc: Shawn Guo Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org --- .../bridge/fsl,imx95-pixel-interleaver.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml new file mode 100644 index 0000000000000..6a0647f060a02 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx95-pixel-interleaver.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX95 Display Pixel Interleaver + +maintainers: + - Liu Ying + - Marek Vasut + +description: | + The Freescale i.MX95 Display Pixel Interleaver receives and processes + 2 input display streams from the display controller and routes those + to 3 pixel link output ports. The interleaver is capable of YUV444 to + YUV422 conversion and pixel interleaving. + +properties: + compatible: + const: fsl,imx95-pixel-interleaver + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers (CSR) module. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link input port node from upstream video source. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link output port node to downstream bridge. + + required: + - port@0 + - port@1 + +required: + - compatible + - fsl,syscon + - ports + +additionalProperties: false + +examples: + - | + bridge@4b0d0000 { + compatible = "fsl,imx95-pixel-interleaver"; + reg = <0x4b0d0000 0x50>; + clocks = <&scmi_clk 0>; + fsl,syscon = <&dispmix_csr>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pixel_interleaver_disp0_to_dpu_disp0: endpoint { + remote-endpoint = <&dpu_disp0_to_pixel_interleaver_disp0>; + }; + }; + + port@1 { + reg = <1>; + + pixel_interleaver_disp0_to_display_pixel_link0: endpoint { + remote-endpoint = <&display_pixel_link0_to_pixel_interleaver_disp0>; + }; + }; + }; + }; -- 2.51.0