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bh=Rxo7qyJjIMTsU/zyVaLPBmGiXTVYD1zzMv1jDaG3HZQ=; b=xaWL2zvr/dMcOzeva3JAPRU9oyXVuiscZJqtWfl1q8bYqzIf8vCUDJINW/ylcmg4lKZSQk 9r4J3wuCV5f6VGcAITfBUlreE0bmtb/bftrZnMfp9tyh9ucyEaUMVHsVblvbgOO98px8Iv z7q+BxIRSc5MFSGvWAM3WdSVdKeOTAmjiMYF7ngmsZPlqtIs4Ku0cEGeiP4eHWPVOmnctl Ur8iEL0JOe9lTEk7jWuHeFToEyc6CK3DiyJJ3XhMOAIwQ0dB9Sb05OFzab2AiSxSd2AM57 zo8WQ854ZBaD9lO/Nk8wVYluXCEtEGdbO/NDGbqWfw3ZaHHMall/q0Us2uRK7A== To: dri-devel@lists.freedesktop.org Cc: Marek Vasut , Abel Vesa , Conor Dooley , Fabio Estevam , Krzysztof Kozlowski , Laurent Pinchart , Liu Ying , Lucas Stach , Peng Fan , Pengutronix Kernel Team , Rob Herring , Shawn Guo , Thomas Zimmermann , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org Subject: [PATCH 27/39] dt-bindings: display: bridge: Document NXP i.MX95 pixel link support Date: Sat, 11 Oct 2025 18:51:42 +0200 Message-ID: <20251011170213.128907-28-marek.vasut@mailbox.org> In-Reply-To: <20251011170213.128907-1-marek.vasut@mailbox.org> References: <20251011170213.128907-1-marek.vasut@mailbox.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-MBO-RS-META: e1iik1smz9zfisk8yowoonbfo69cicwa X-MBO-RS-ID: cecf55de22ea7313ca3 X-Rspamd-Queue-Id: 4ckVMF2VNpz9stk X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251011_101435_715632_F2AAC6AD X-CRM114-Status: GOOD ( 11.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Document NXP i.MX95 pixel link bridge support. Signed-off-by: Marek Vasut --- Cc: Abel Vesa Cc: Conor Dooley Cc: Fabio Estevam Cc: Krzysztof Kozlowski Cc: Laurent Pinchart Cc: Liu Ying Cc: Lucas Stach Cc: Peng Fan Cc: Pengutronix Kernel Team Cc: Rob Herring Cc: Shawn Guo Cc: Thomas Zimmermann Cc: devicetree@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Cc: linux-clk@vger.kernel.org --- .../display/bridge/fsl,imx95-pixel-link.yaml | 101 ++++++++++++++++++ 1 file changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml new file mode 100644 index 0000000000000..b37888adfa45e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-link.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx95-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX95 Display Pixel Link + +maintainers: + - Liu Ying + - Marek Vasut + +description: | + The Freescale i.MX95 Display Pixel Link (DPL) forms a standard + asynchronous linkage between pixel sources (display controller + or camera module) and pixel consumers(imaging or displays). + It consists of two distinct functions, a pixel transfer function + and a control interface. Multiple pixel channels can exist per one + control channel. This binding documentation is only for pixel links + whose pixel sources are display controllers. + + The i.MX95 Display Pixel Link is accessed via syscon. + +properties: + compatible: + const: fsl,imx95-dc-pixel-link + + fsl,dc-stream-id: + $ref: /schemas/types.yaml#/definitions/uint8 + description: | + u8 value representing the display controller stream index that the pixel + link connects to. + enum: [0, 1] + + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers (CSR) module. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link input port node from upstream video source. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link output port node to downstream bridge. + + required: + - port@0 + - port@1 + +required: + - compatible + - fsl,dc-stream-id + - fsl,syscon + - ports + +additionalProperties: false + +examples: + - | + dc0-pixel-link0 { + compatible = "fsl,imx95-dc-pixel-link"; + fsl,dc-stream-id = /bits/ 8 <0>; + fsl,syscon = <&dispmix_csr>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* from DC 0 pixel interleaver channel0 */ + port@0 { + reg = <0>; + + dc0_pixel_link0_dc0_pixel_interleaver_ch0: endpoint { + remote-endpoint = <&dc0_pixel_interleaver_ch0_dc0_pixel_link0>; + }; + }; + + /* to MIPI/LVDS combo subsystems */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; + }; + + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; + }; + }; + }; + }; -- 2.51.0