From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9F4D2CCD184 for ; Sun, 12 Oct 2025 19:24:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=aDedyHXZRi05h+yiSLUF3HPKeqGWy/zcBT6LVM4ULn4=; b=vrP676Qr5Tj3ooc052yWoA181L ePmneN417AAziMYc1vpM58HYJV15PJEuEKCxGO6SVtf40nZFVDMmlvdKOKsCI9ngebBED9WxYh++4 ixKx4ycdZFD7oV0dA/ZLam86XwdMj55iX34dEcYa2+3mKCyCzOwBUstCcLKwbwQOVkFyENg8kxbSp wYJO1Sk0h7n+ClXaBeQN8JSm3Tep1D3LgnpWYQ73WhFWqosEBUqs/0KfcYC/Voe0tcgCdqjQJiGrT 7jd8Q6/xiUPYWOZiCRSFz2OaWZLGzPQ1qbkq/e4Y4CPSByWhWkZbuNAuPIWHmHCpFt0Y32uPL+B4e QnFXPV+w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1v81gM-0000000BghL-1vBS; Sun, 12 Oct 2025 19:24:38 +0000 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1v81fq-0000000BfvP-0e2S for linux-arm-kernel@lists.infradead.org; Sun, 12 Oct 2025 19:24:09 +0000 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-634b774f135so5723416a12.2 for ; Sun, 12 Oct 2025 12:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1760297044; x=1760901844; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aDedyHXZRi05h+yiSLUF3HPKeqGWy/zcBT6LVM4ULn4=; b=kwCQMuNU5T4l2t3QljPfRAsUEwl6aqg9zMxYu7XX8x9Yq2yOKwI1ndgd1myamliKWd TK5NUCw10kXiMeR2lZ/LuoaWcExAalfHzKw/Fd1+1G9TAtitj1dmwBNOqX+Pm2W6OjAt xT9bmcrN0L1avZKTO1LDtxcC980u8ZT3yeEdgzGfl9MvtOUJKlo5LTSQU+i36TYFMNDV RQKEtUDtZLQ95x61TiBVPVDzGrhI+uos+gLE/z4CJ8onH40WK9Lp7VmVyWjc7NOQxspy zE25HEXN0/sJDzvQ6kgKKtZv761oStdCz21Q2RB9RmhI0UklQvVqrmu79ATQabpUgT7F xlOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1760297044; x=1760901844; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aDedyHXZRi05h+yiSLUF3HPKeqGWy/zcBT6LVM4ULn4=; b=gZ1C0oo7tKJZXPFhVWpe4r3Rjk83xOHqJn3HM93o9aAuMUXCWGwhhypuPUhcbTm9gZ I7MHF15EVtiBPXPJfnJKDP2b6h6x8NjkIEI2C4WJ0tgx/XYrrmRjJNaiLdoFJN9FK+sM S3wLAj0GzJUShOrdC00qKl9RxNYwp3J+uV/lc9t398pbkqQ1ZNgPkNwToEI3tGr2VghI n71KHXqjpJH4/WSNmwS1AFTuvApMSoum5Qv6Larr4Mci6Sulyt4XvAdRKAuY8je4ZEVY L8gdjsDGt8vX1eZ/Pmw02HzqNOomcyZfONR/pH7plRSJVY3sVOdrQ5YIHuiXLX6K+hfI +gng== X-Forwarded-Encrypted: i=1; AJvYcCWqfMticquwckRKJnKK6LCDUV/R5iifGzNxQ6lQfDv4JO5uCLY0pAzdP/ocYELGfsJRxOoK75WP6l9I1tq5ynVx@lists.infradead.org X-Gm-Message-State: AOJu0Yyi9HRApvBs1vL8tZHe+dMRbV7w+PcyQ9TVgwnh3HTpYwftTl3C NiuLrRJkRd2sHwUI2SfavKCMXgynMV/3Z+O0gVKIPd9bsJNgDYvAWeqm X-Gm-Gg: ASbGncv6PHxKhHlglEzEmpoyqswe+BcAnpQHk1EVieMP/EDgo+0x0q/48OwCeAG3KC5 b9r6rckiDuXm5WHEFabN/yWiHcbiMwTWp1SEjwBrUJG9zd8ihFjm4LTPmYn60qhBt3miyppw2lm MkSzKBCo9ckapq8UWlgkFibSE0KToZmPGEIR/PVy/K0XXNANAFkniZbbJgRO/qj3qBy58VRQ4w2 RsVdSthEYp467Ua+yzHJQ18lZDH7RTlLoc30BW5NlAKSklAMlzMvsaku5BBv5yX6XZBBYbv8b9S BqJDqHHgtqvpFDIv3hpXs9M0Dk6B6hAtyBeCaPfLsycRA3JnwG1hHl/xHl1SFjHIQGbxGKtu0dR qYJdzo9y+NPVs+4o6/8x9c4WpUL7498uu6++DT3v1RrkHCh3A0YypPkBPGRzb2iW2JL1XnKBELr HuLtKnCe9o38xWETZKoehSCc5fTzI2jFI= X-Google-Smtp-Source: AGHT+IExRv+GMaQElZOiBYi8D06q1t4JtHvZ0OQ67C2+WOBYzOxOgvcGPMSugeMHawmkzgGhW4vqWA== X-Received: by 2002:a17:907:3e16:b0:b04:67f3:890f with SMTP id a640c23a62f3a-b50ac1d014dmr2008689366b.33.1760297043846; Sun, 12 Oct 2025 12:24:03 -0700 (PDT) Received: from jernej-laptop (178-79-73-218.dynamic.telemach.net. [178.79.73.218]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b55d67d8283sm760176466b.38.2025.10.12.12.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Oct 2025 12:24:03 -0700 (PDT) From: Jernej Skrabec To: mripard@kernel.org, wens@csie.org Cc: maarten.lankhorst@linux.intel.com, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, samuel@sholland.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Jernej Skrabec Subject: [PATCH 20/30] drm/sun4i: layers: Make regmap for layers configurable Date: Sun, 12 Oct 2025 21:23:20 +0200 Message-ID: <20251012192330.6903-21-jernej.skrabec@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251012192330.6903-1-jernej.skrabec@gmail.com> References: <20251012192330.6903-1-jernej.skrabec@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251012_122406_319799_98463A19 X-CRM114-Status: GOOD ( 17.69 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Till DE33, there were no reason to decouple registers from mixer. However, with future new plane driver, this will be necessary. Signed-off-by: Jernej Skrabec --- drivers/gpu/drm/sun4i/sun8i_mixer.c | 7 ++++-- drivers/gpu/drm/sun4i/sun8i_mixer.h | 1 + drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 12 ++++++---- drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 1 + drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 16 ++++++------- drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 22 ++++++++++-------- drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 1 + drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 31 ++++++++++++------------- 8 files changed, 50 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index 18dd998364ae..d2b7fc552a76 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -331,7 +331,9 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, else type = DRM_PLANE_TYPE_OVERLAY; - layer = sun8i_vi_layer_init_one(drm, mixer, type, i, plane_cnt); + layer = sun8i_vi_layer_init_one(drm, mixer, type, + mixer->engine.regs, i, + plane_cnt); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize overlay plane\n"); @@ -350,7 +352,8 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm, else type = DRM_PLANE_TYPE_OVERLAY; - layer = sun8i_ui_layer_init_one(drm, mixer, type, index, + layer = sun8i_ui_layer_init_one(drm, mixer, type, + mixer->engine.regs, index, plane_cnt); if (IS_ERR(layer)) { dev_err(drm->dev, "Couldn't initialize %s plane\n", diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h index b5badfa2c997..2e3689008b50 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h @@ -214,6 +214,7 @@ struct sun8i_layer { int type; int channel; int overlay; + struct regmap *regs; }; static inline struct sun8i_layer * diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c index 5167c9d7b9c0..dd6cb09c2c01 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c @@ -53,7 +53,7 @@ static void sun8i_ui_layer_update_attributes(struct sun8i_layer *layer, val |= hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; val |= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, layer->overlay), val); } @@ -87,10 +87,10 @@ static void sun8i_ui_layer_update_coord(struct sun8i_layer *layer, DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", state->src.x1 >> 16, state->src.y1 >> 16); DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, layer->overlay), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base), insize); @@ -149,13 +149,13 @@ static void sun8i_ui_layer_update_buffer(struct sun8i_layer *layer, /* Set the line width */ DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, layer->overlay), fb->pitches[0]); DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &dma_addr); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, layer->overlay), lower_32_bits(dma_addr)); } @@ -264,6 +264,7 @@ static const uint64_t sun8i_layer_modifiers[] = { struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt) { @@ -278,6 +279,7 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, layer->type = SUN8I_LAYER_TYPE_UI; layer->channel = index; layer->overlay = 0; + layer->regs = regs; /* possible crtcs are set later */ ret = drm_universal_plane_init(drm, &layer->plane, 0, diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h index 0613b34d36e0..e0b2cfa02749 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h +++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h @@ -52,6 +52,7 @@ struct sun8i_layer; struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt); #endif /* _SUN8I_UI_LAYER_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c index fcd72c4fd49a..2fc54dc20307 100644 --- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c +++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c @@ -143,7 +143,7 @@ void sun8i_ui_scaler_enable(struct sun8i_layer *layer, bool enable) else val = 0; - regmap_write(mixer->engine.regs, SUN8I_SCALER_GSU_CTRL(base), val); + regmap_write(layer->regs, SUN8I_SCALER_GSU_CTRL(base), val); } void sun8i_ui_scaler_setup(struct sun8i_layer *layer, @@ -168,22 +168,22 @@ void sun8i_ui_scaler_setup(struct sun8i_layer *layer, insize = SUN8I_UI_SCALER_SIZE(src_w, src_h); outsize = SUN8I_UI_SCALER_SIZE(dst_w, dst_h); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_OUTSIZE(base), outsize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_INSIZE(base), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_HSTEP(base), hscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_VSTEP(base), vscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_HPHASE(base), hphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_VPHASE(base), vphase); offset = sun8i_ui_scaler_coef_index(hscale) * SUN8I_UI_SCALER_COEFF_COUNT; for (i = 0; i < SUN8I_UI_SCALER_COEFF_COUNT; i++) - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_GSU_HCOEFF(base, i), lan2coefftab16[offset + i]); } diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c index ce71625fa06f..2290c983e177 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c @@ -49,12 +49,12 @@ static void sun8i_vi_layer_update_attributes(struct sun8i_layer *layer, SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_PIXEL : SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_COMBINED; } else if (mixer->cfg->vi_num == 1) { - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_FCC_GLOBAL_ALPHA_REG, SUN8I_MIXER_FCC_GLOBAL_ALPHA(state->alpha >> 8)); } - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, layer->overlay), val); } @@ -112,10 +112,10 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer, (state->src.x1 >> 16) & ~(format->hsub - 1), (state->src.y1 >> 16) & ~(format->vsub - 1)); DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_SIZE(ch_base, layer->overlay), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_OVL_SIZE(ch_base), insize); @@ -170,19 +170,19 @@ static void sun8i_vi_layer_update_coord(struct sun8i_layer *layer, sun8i_vi_scaler_enable(layer, false); } - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_HDS_Y(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(hn) | SUN8I_MIXER_CHAN_VI_DS_M(hm)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_HDS_UV(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(hn) | SUN8I_MIXER_CHAN_VI_DS_M(hm)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_VDS_Y(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(vn) | SUN8I_MIXER_CHAN_VI_DS_M(vm)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_VDS_UV(ch_base), SUN8I_MIXER_CHAN_VI_DS_N(vn) | SUN8I_MIXER_CHAN_VI_DS_M(vm)); @@ -231,7 +231,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer, /* Set the line width */ DRM_DEBUG_DRIVER("Layer %d. line width: %d bytes\n", i + 1, fb->pitches[i]); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_PITCH(ch_base, layer->overlay, i), fb->pitches[i]); @@ -239,7 +239,7 @@ static void sun8i_vi_layer_update_buffer(struct sun8i_layer *layer, DRM_DEBUG_DRIVER("Setting %d. buffer address to %pad\n", i + 1, &dma_addr); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(ch_base, layer->overlay, i), lower_32_bits(dma_addr)); @@ -410,6 +410,7 @@ static const uint64_t sun8i_layer_modifiers[] = { struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt) { @@ -427,6 +428,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, layer->type = SUN8I_LAYER_TYPE_VI; layer->channel = index; layer->overlay = 0; + layer->regs = regs; if (mixer->cfg->de_type >= SUN8I_MIXER_DE3) { formats = sun8i_vi_layer_de3_formats; diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h index a568e1db1e19..70766d752fa6 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.h +++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.h @@ -57,6 +57,7 @@ struct sun8i_layer; struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm, struct sun8i_mixer *mixer, enum drm_plane_type type, + struct regmap *regs, int index, int plane_cnt); #endif /* _SUN8I_VI_LAYER_H_ */ diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c index a76677a1649f..0e308feb492a 100644 --- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c +++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c @@ -911,10 +911,9 @@ static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base, void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable) { - struct sun8i_mixer *mixer = layer->mixer; u32 val, base; - base = sun8i_vi_scaler_base(mixer, layer->channel); + base = sun8i_vi_scaler_base(layer->mixer, layer->channel); if (enable) val = SUN8I_SCALER_VSU_CTRL_EN | @@ -922,7 +921,7 @@ void sun8i_vi_scaler_enable(struct sun8i_layer *layer, bool enable) else val = 0; - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CTRL(base), val); } @@ -968,36 +967,36 @@ void sun8i_vi_scaler_setup(struct sun8i_layer *layer, else val = SUN50I_SCALER_VSU_SCALE_MODE_NORMAL; - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN50I_SCALER_VSU_SCALE_MODE(base), val); } - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_OUTSIZE(base), outsize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YINSIZE(base), insize); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YHSTEP(base), hscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YVSTEP(base), vscale); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YHPHASE(base), hphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_YVPHASE(base), vphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CINSIZE(base), SUN8I_VI_SCALER_SIZE(src_w / format->hsub, src_h / format->vsub)); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CHSTEP(base), hscale / format->hsub); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CVSTEP(base), vscale / format->vsub); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CHPHASE(base), chphase); - regmap_write(mixer->engine.regs, + regmap_write(layer->regs, SUN8I_SCALER_VSU_CVPHASE(base), cvphase); - sun8i_vi_scaler_set_coeff(mixer->engine.regs, base, + sun8i_vi_scaler_set_coeff(layer->regs, base, hscale, vscale, format); } -- 2.51.0