[PATCH v3 0/2] arm64: dts: rockchip: Add vdpu 381 and 383 nodes

[PATCH v3 0/2] arm64: dts: rockchip: Add vdpu 381 and 383 nodes

[Detlev Casanova]

Add the nodes for vdpu 381 and 383, respectively RK3588 and RK3576.
To keep compatibility with older variants, the reg ranges order is not
in register order so that the function reg range is kept first.

Also adds the corresponding iommu nodes.

Note that on RK3588, both cores are added as it represents the hardware,
but the driver, later will only register the first one.

Regards,
Detlev.

Changes since v2:
 - Set the correct IRQ number for the second rk3588 core

Changes since v1:
 - Set node name to match first reg range

Detlev Casanova (2):
  arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588
  arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576

 arch/arm64/boot/dts/rockchip/rk3576.dtsi      | 36 +++++++++
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
 2 files changed, 110 insertions(+)

-- 
2.51.1.dirty

[PATCH v3 1/2] arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588

[Detlev Casanova]

Add the vdpu381 Video Decoders to the rk3588-base devicetree.

The RK3588 based SoCs all embed 2 vdpu381 decoders.
This also adds the dedicated IOMMU controllers.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index e2500e31c434..d076267a330b 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1353,6 +1353,70 @@ vepu121_3_mmu: iommu@fdbac800 {
 		#iommu-cells = <0>;
 	};
 
+	vdec0: video-codec@fdc38000 {
+		compatible = "rockchip,rk3588-vdec";
+		reg = <0x0 0xfdc38100 0x0 0x500>,
+		      <0x0 0xfdc38000 0x0 0x100>,
+		      <0x0 0xfdc38600 0x0 0x100>;
+		reg-names = "function", "link", "cache";
+		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
+			 <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
+		clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+		assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>,
+				  <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>;
+		assigned-clock-rates = <800000000>, <600000000>,
+				       <600000000>, <1000000000>;
+		iommus = <&vdec0_mmu>;
+		power-domains = <&power RK3588_PD_RKVDEC0>;
+		resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CA>,
+			 <&cru SRST_RKVDEC0_CORE>, <&cru SRST_RKVDEC0_HEVC_CA>;
+		reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+		sram = <&vdec0_sram>;
+	};
+
+	vdec0_mmu: iommu@fdc38700 {
+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+		reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>;
+		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RK3588_PD_RKVDEC0>;
+		#iommu-cells = <0>;
+	};
+
+	vdec1: video-codec@fdc40000 {
+		compatible = "rockchip,rk3588-vdec";
+		reg = <0x0 0xfdc40100 0x0 0x500>,
+		      <0x0 0xfdc40000 0x0 0x100>,
+		      <0x0 0xfdc40600 0x0 0x100>;
+		reg-names = "function", "link", "cache";
+		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
+			 <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
+		clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+		assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>,
+				  <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>;
+		assigned-clock-rates = <800000000>, <600000000>,
+				       <600000000>, <1000000000>;
+		iommus = <&vdec1_mmu>;
+		power-domains = <&power RK3588_PD_RKVDEC1>;
+		resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CA>,
+			 <&cru SRST_RKVDEC1_CORE>, <&cru SRST_RKVDEC1_HEVC_CA>;
+		reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+		sram = <&vdec1_sram>;
+	};
+
+	vdec1_mmu: iommu@fdc40700 {
+		compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu";
+		reg = <0x0 0xfdc40700 0x0 0x40>, <0x0 0xfdc40740 0x0 0x40>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
+		clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>;
+		clock-names = "aclk", "iface";
+		power-domains = <&power RK3588_PD_RKVDEC1>;
+		#iommu-cells = <0>;
+	};
+
 	av1d: video-codec@fdc70000 {
 		compatible = "rockchip,rk3588-av1-vpu";
 		reg = <0x0 0xfdc70000 0x0 0x800>;
@@ -3248,6 +3312,16 @@ system_sram2: sram@ff001000 {
 		ranges = <0x0 0x0 0xff001000 0xef000>;
 		#address-cells = <1>;
 		#size-cells = <1>;
+
+		vdec0_sram: codec-sram@0 {
+			reg = <0x0 0x78000>;
+			pool;
+		};
+
+		vdec1_sram: codec-sram@78000 {
+			reg = <0x78000 0x77000>;
+			pool;
+		};
 	};
 
 	pinctrl: pinctrl {
-- 
2.51.1.dirty

[PATCH v3 2/2] arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576

[Detlev Casanova]

Add the vdpu383 Video Decoder variant to the RK3576 device tree.

Also allow using the dedicated SRAM as a pool.

Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
---
 arch/arm64/boot/dts/rockchip/rk3576.dtsi | 36 ++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index fc4e9e07f1cf..00999823746f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1289,6 +1289,41 @@ gpu: gpu@27800000 {
 			status = "disabled";
 		};
 
+		vdec: video-codec@27b00000 {
+			compatible = "rockchip,rk3576-vdec";
+			reg = <0x0 0x27b00100 0x0 0x500>,
+			      <0x0 0x27b00000 0x0 0x100>,
+			      <0x0 0x27b00600 0x0 0x100>;
+			reg-names = "function", "link", "cache";
+			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
+				 <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,
+				 <&cru CLK_RKVDEC_HEVC_CA>;
+			clock-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+			assigned-clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru CLK_RKVDEC_CORE>,
+					  <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_HEVC_CA>;
+			assigned-clock-rates = <600000000>, <600000000>,
+					       <500000000>, <1000000000>;
+			iommus = <&vdec_mmu>;
+			power-domains = <&power RK3576_PD_VDEC>;
+			resets = <&cru SRST_A_RKVDEC_BIU>, <&cru SRST_H_RKVDEC_BIU>,
+				 <&cru SRST_H_RKVDEC>, <&cru SRST_RKVDEC_CORE>,
+				 <&cru SRST_RKVDEC_HEVC_CA>;
+			reset-names = "axi", "ahb", "cabac", "core", "hevc_cabac";
+			sram = <&rkvdec_sram>;
+		};
+
+		vdec_mmu: iommu@27b00800 {
+			compatible = "rockchip,rk3576-iommu", "rockchip,rk3568-iommu";
+			reg = <0x0 0x27b00800 0x0 0x40>, <0x0 0x27b00900 0x0 0x40>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cru CLK_RKVDEC_CORE>, <&cru HCLK_RKVDEC>;
+			clock-names = "aclk", "iface";
+			power-domains = <&power RK3576_PD_VDEC>;
+			rockchip,disable-mmu-reset;
+			#iommu-cells = <0>;
+		};
+
 		vop: vop@27d00000 {
 			compatible = "rockchip,rk3576-vop";
 			reg = <0x0 0x27d00000 0x0 0x3000>, <0x0 0x27d05000 0x0 0x1000>;
@@ -2694,6 +2729,7 @@ sram: sram@3ff88000 {
 			/* start address and size should be 4k align */
 			rkvdec_sram: rkvdec-sram@0 {
 				reg = <0x0 0x78000>;
+				pool;
 			};
 		};
 
-- 
2.51.1.dirty

Re: [PATCH v3 0/2] arm64: dts: rockchip: Add vdpu 381 and 383 nodes

[Diederik de Haas]

Hi Detlev,

On Mon Oct 20, 2025 at 11:20 PM CEST, Detlev Casanova wrote:
> Add the nodes for vdpu 381 and 383, respectively RK3588 and RK3576.
> To keep compatibility with older variants, the reg ranges order is not
> in register order so that the function reg range is kept first.

This is a great comment, which I'd have preferred to have seen in the
commit messages themselves.

Especially since I'm getting DTB validation warnings:

  DTC [C] arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dtb
arch/arm64/boot/dts/rockchip/rk3576.dtsi:1292.30-1314.5: Warning (simple_bus_reg):
/soc/video-codec@27b00000: simple-bus unit address format error, expected "27b00100"
  DTC [C] arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dtb
arch/arm64/boot/dts/rockchip/rk3576.dtsi:1292.30-1314.5: Warning (simple_bus_reg):
/soc/video-codec@27b00000: simple-bus unit address format error, expected "27b00100"


For some reason I'm not getting that for rk3588, which I need to
investigate further. Technically, I ran my DTB validation script on your
'add-vdpu381-and-383-to-rkvdec-v3-on-next' branch, but I don't see how
that would/could change the outcome.

My validation script does essentially this:
``make CHECK_DTBS=y W=1 $(get_my_dtbs)``

('get_my_dtbs' returns a list of dtb files I want to check)

So it looks like the DTB validation tool is not happy that the
reg ranges are not sorted in 'proper' order.

Note that the ``W=1`` is essential to see the warning, it does not show
up when ``W=0`` is used.
I'll leave it up to you and the maintainers to judge whether this is
problematic or not, but wanted to mention it.

Cheers,
  Diederik

> Also adds the corresponding iommu nodes.
>
> Note that on RK3588, both cores are added as it represents the hardware,
> but the driver, later will only register the first one.
>
> Regards,
> Detlev.
>
> Changes since v2:
>  - Set the correct IRQ number for the second rk3588 core
>
> Changes since v1:
>  - Set node name to match first reg range
>
> Detlev Casanova (2):
>   arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588
>   arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576
>
>  arch/arm64/boot/dts/rockchip/rk3576.dtsi      | 36 +++++++++
>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
>  2 files changed, 110 insertions(+)

Re: [PATCH v3 0/2] arm64: dts: rockchip: Add vdpu 381 and 383 nodes

[Detlev Casanova]

Hi Diederick,

On 10/24/25 15:20, Diederik de Haas wrote:
> Hi Detlev,
>
> On Mon Oct 20, 2025 at 11:20 PM CEST, Detlev Casanova wrote:
>> Add the nodes for vdpu 381 and 383, respectively RK3588 and RK3576.
>> To keep compatibility with older variants, the reg ranges order is not
>> in register order so that the function reg range is kept first.
> This is a great comment, which I'd have preferred to have seen in the
> commit messages themselves.
>
> Especially since I'm getting DTB validation warnings:
>
>    DTC [C] arch/arm64/boot/dts/rockchip/rk3576-armsom-sige5.dtb
> arch/arm64/boot/dts/rockchip/rk3576.dtsi:1292.30-1314.5: Warning (simple_bus_reg):
> /soc/video-codec@27b00000: simple-bus unit address format error, expected "27b00100"
>    DTC [C] arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dtb
> arch/arm64/boot/dts/rockchip/rk3576.dtsi:1292.30-1314.5: Warning (simple_bus_reg):
> /soc/video-codec@27b00000: simple-bus unit address format error, expected "27b00100"
>
>
> For some reason I'm not getting that for rk3588, which I need to
> investigate further. Technically, I ran my DTB validation script on your
> 'add-vdpu381-and-383-to-rkvdec-v3-on-next' branch, but I don't see how
> that would/could change the outcome.
>
> My validation script does essentially this:
> ``make CHECK_DTBS=y W=1 $(get_my_dtbs)``
>
> ('get_my_dtbs' returns a list of dtb files I want to check)
>
> So it looks like the DTB validation tool is not happy that the
> reg ranges are not sorted in 'proper' order.
>
> Note that the ``W=1`` is essential to see the warning, it does not show
> up when ``W=0`` is used.
> I'll leave it up to you and the maintainers to judge whether this is
> problematic or not, but wanted to mention it.

The main reason for doing it this way is that the bindings are added to 
the already existing media/rockchip,vdec.yaml file.

In the previous version of the decoder, only the "function" registers 
existed. But in these 2 SoCs, the function registers are prepended by a 
range of 0x100 registers called "link".

At the binding level, I only could add "link" and "cache" after 
"function", so that rk3399 uses "maxItems: 1" and the other 2 use 
"minItems: 3".

Unfortunately, that forces the order in the device tree:

- function

- link

-cache

Which is not in register offset order, making the node called 
video-codec@27b00000 have its first reg entry at 27b00100.

I have to admit I only checked that the check tools were happy for 
rk3588 and did the same for rk3576.

The only difference I see that could explain why it warns only on rk356 
is that rk3576 device nodes are children of "/soc" and the rk3588 ones 
are children of "/".

Let's see what maintainers think indeed.


Detlev.

>
> Cheers,
>    Diederik

>> Also adds the corresponding iommu nodes.
>>
>> Note that on RK3588, both cores are added as it represents the hardware,
>> but the driver, later will only register the first one.
>>
>> Regards,
>> Detlev.
>>
>> Changes since v2:
>>   - Set the correct IRQ number for the second rk3588 core
>>
>> Changes since v1:
>>   - Set node name to match first reg range
>>
>> Detlev Casanova (2):
>>    arm64: dts: rockchip: Add the vdpu381 Video Decoders on RK3588
>>    arm64: dts: rockchip: Add the vdpu383 Video Decoder on rk3576
>>
>>   arch/arm64/boot/dts/rockchip/rk3576.dtsi      | 36 +++++++++
>>   arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 74 +++++++++++++++++++
>>   2 files changed, 110 insertions(+)
>
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