From: Conor Dooley <conor@kernel.org>
To: Gary Yang <gary.yang@cixtech.com>
Cc: linus.walleij@linaro.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, linux-gpio@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
cix-kernel-upstream@cixtech.com
Subject: Re: [PATCH v5 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl
Date: Wed, 22 Oct 2025 18:44:50 +0100 [thread overview]
Message-ID: <20251022-flammable-mockup-4965b730e86b@spud> (raw)
In-Reply-To: <20251021070410.3585997-2-gary.yang@cixtech.com>
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On Tue, Oct 21, 2025 at 03:04:08PM +0800, Gary Yang wrote:
> The pin-controller is used to control the Soc pins.
> There are two pin-controllers on Cix Sky1 platform.
> One is used under S0 state, the other is used under
> S0 and S5 state.
>
> Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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next prev parent reply other threads:[~2025-10-22 17:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 7:04 [PATCH v5 0/3] Add pinctrl support for Sky1 Gary Yang
2025-10-21 7:04 ` [PATCH v5 1/3] dt-bindings: pinctrl: Add cix,sky1-pinctrl Gary Yang
2025-10-22 17:44 ` Conor Dooley [this message]
2025-10-21 7:04 ` [PATCH v5 2/3] pinctrl: cix: Add pin-controller support for sky1 Gary Yang
2025-10-21 7:04 ` [PATCH v5 3/3] arm64: dts: cix: Add pinctrl nodes " Gary Yang
2025-10-28 6:08 ` Peter Chen
2025-10-27 21:56 ` [PATCH v5 0/3] Add pinctrl support for Sky1 Linus Walleij
2025-10-28 1:04 ` Peter Chen
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