From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E7E1ECCD1AB for ; Wed, 22 Oct 2025 21:39:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=wc5x1Gwl3C0XgAlO395LUopwk5B3TtKZafU21IA+ndQ=; b=krAgL8nHIf1Oj838iBO1fFvxnb 2kdCaIAKNOkaSdzMRpsX8GQyAXcOP0F/QJijfO14OtvFYJkKC2g7kOBUL9WFCNyl8boH4tAKqTKTf HpmMV4gnUeezx7MiylaAhCXnYOXrOEeZqcjEAqlvQnv+B9NNzqYXD26yVTnNiANXp5Xc66IBdm+58 TnYiTIs7tZdXNgkbMEoF/132H/nWwcky0CzotVHmXyisHJpLYJvKnqm14fCgr2jayUVPaFtUw0Z/+ 5PgNmujmveCGyTOMIVDTheYu2zZgYVCcJij6MIswF8VS44tITN1nrBb3IKoNoiQNHvDoUExseZsWt eP9ctdcg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vBgYT-00000004NUV-3W7Y; Wed, 22 Oct 2025 21:39:37 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vBgYS-00000004NTy-1uxx for linux-arm-kernel@lists.infradead.org; Wed, 22 Oct 2025 21:39:36 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id C104663E1E; Wed, 22 Oct 2025 21:39:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1B0F7C4CEE7; Wed, 22 Oct 2025 21:39:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1761169175; bh=fMnDUsh++hTRlW5dn4gfNo7HgWB7+StricBM3MTmevE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=HNWwA7uT41H1QeC3nDJKzxGOAYopyZyz8wtaReHnMFNDClB7pEowhjPcwr/h555lQ jVxtk2LwgDfOBrV2C1kpcI5K4L/QQTXZdNgUl0O4FXSwDIIJZ6hxJeud2yNdpiq/+M 8EJBosY1IHyBF2qbURoZ+X8CZjQ1U95UUYYKemkTqV1JzCIfJyset7oaAlrfKF4mF4 WbVDphXvbnCpZ3IipJhwoV0ZsefssffeUcgsW59U02F+Q8u5G2n+rXOzbnD6+eMX57 jtCI+BMlMh63VWOMWxICaIOtULATYu3+pTOojxsVyRsl+O/sHbxAPjROCsiuLpTAhk +aIwx9oysP7iA== Date: Wed, 22 Oct 2025 22:39:28 +0100 From: Conor Dooley To: Jonathan Cameron Cc: Catalin Marinas , linux-cxl@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, Dan Williams , "H . Peter Anvin" , Peter Zijlstra , Andrew Morton , james.morse@arm.com, Will Deacon , Davidlohr Bueso , linuxarm@huawei.com, Yushan Wang , Lorenzo Pieralisi , Mark Rutland , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, Andy Lutomirski , Dave Jiang Subject: Re: [PATCH v4 6/6] cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent Message-ID: <20251022-kite-revert-2c2684054d05@spud> References: <20251022113349.1711388-1-Jonathan.Cameron@huawei.com> <20251022113349.1711388-7-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="Hs5fF3jxcDKPxATt" Content-Disposition: inline In-Reply-To: <20251022113349.1711388-7-Jonathan.Cameron@huawei.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --Hs5fF3jxcDKPxATt Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Oct 22, 2025 at 12:33:49PM +0100, Jonathan Cameron wrote: > +static int hisi_soc_hha_wbinv(struct cache_coherency_ops_inst *cci, > + struct cc_inval_params *invp) > +{ > + struct hisi_soc_hha *soc_hha =3D > + container_of(cci, struct hisi_soc_hha, cci); > + phys_addr_t top, addr =3D invp->addr; > + size_t size =3D invp->size; > + u32 reg; > + > + if (!size) > + return -EINVAL; > + > + addr =3D ALIGN_DOWN(addr, HISI_HHA_MAINT_ALIGN); > + top =3D ALIGN(addr + size, HISI_HHA_MAINT_ALIGN); > + size =3D top - addr; > + > + guard(mutex)(&soc_hha->lock); > + > + if (!hisi_hha_cache_maintain_wait_finished(soc_hha)) > + return -EBUSY; > + > + /* > + * Hardware will search for addresses ranging [addr, addr + size - 1], > + * last byte included, and perform maintain in 128 byte granule > + * on those cachelines which contain the addresses. > + */ Hmm, does this mean that the IP has some built-in handling for there being more than one "agent" in a system? IOW, if the address is not in its range, then the search will just fail into a NOP? If that's not the case, is this particular "agent" by design not suitable for a system like that? Or will a dual hydra home agent system come with a new ACPI ID that we can use to deal with that kind of situation? (Although I don't know enough about ACPI to know where you'd even get the information about what instance handles what range from...) > + size -=3D 1; > + > + writel(lower_32_bits(addr), soc_hha->base + HISI_HHA_START_L); > + writel(upper_32_bits(addr), soc_hha->base + HISI_HHA_START_H); > + writel(lower_32_bits(size), soc_hha->base + HISI_HHA_LEN_L); > + writel(upper_32_bits(size), soc_hha->base + HISI_HHA_LEN_H); > + > + reg =3D FIELD_PREP(HISI_HHA_CTRL_TYPE, 1); /* Clean Invalid */ > + reg |=3D HISI_HHA_CTRL_RANGE | HISI_HHA_CTRL_EN; > + writel(reg, soc_hha->base + HISI_HHA_CTRL); > + > + return 0; > +} > + > +static int hisi_soc_hha_done(struct cache_coherency_ops_inst *cci) > +{ > + struct hisi_soc_hha *soc_hha =3D > + container_of(cci, struct hisi_soc_hha, cci); > + > + guard(mutex)(&soc_hha->lock); > + if (!hisi_hha_cache_maintain_wait_finished(soc_hha)) > + return -ETIMEDOUT; > + > + return 0; > +} > + > +static const struct cache_coherency_ops hha_ops =3D { > + .wbinv =3D hisi_soc_hha_wbinv, > + .done =3D hisi_soc_hha_done, > +}; > + > +static int hisi_soc_hha_probe(struct platform_device *pdev) > +{ > + struct hisi_soc_hha *soc_hha; > + struct resource *mem; > + int ret; > + > + soc_hha =3D cache_coherency_ops_instance_alloc(&hha_ops, > + struct hisi_soc_hha, cci); > + if (!soc_hha) > + return -ENOMEM; > + > + platform_set_drvdata(pdev, soc_hha); > + > + mutex_init(&soc_hha->lock); > + > + mem =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!mem) { > + ret =3D -ENOMEM; > + goto err_free_cci; > + } > + > + /* > + * HHA cache driver share the same register region with HHA uncore PMU > + * driver in hardware's perspective, none of them should reserve the > + * resource to itself only. Here exclusive access verification is > + * avoided by calling devm_ioremap instead of devm_ioremap_resource to The comment here doesn't exactly match the code, dunno if you went away =66rom devm some reason and just forgot to to make the change or the other way around? Not a big deal obviously, but maybe you forgot to do something you intended doing. It's mentioned in the commit message too. Other than the question I have about the multi-"agent" stuff, this looks fine to me. I assume it's been thought about and is fine for w/e reason, but I'd like to know what that is. Cheers, Conor. > + * allow both drivers to exist at the same time. > + */ > + soc_hha->base =3D ioremap(mem->start, resource_size(mem)); > + if (!soc_hha->base) { > + ret =3D dev_err_probe(&pdev->dev, -ENOMEM, > + "failed to remap io memory"); > + goto err_free_cci; > + } > + > + ret =3D cache_coherency_ops_instance_register(&soc_hha->cci); > + if (ret) > + goto err_iounmap; > + > + return 0; > + > +err_iounmap: > + iounmap(soc_hha->base); > +err_free_cci: > + cache_coherency_ops_instance_put(&soc_hha->cci); > + return ret; > +} > + > +static void hisi_soc_hha_remove(struct platform_device *pdev) > +{ > + struct hisi_soc_hha *soc_hha =3D platform_get_drvdata(pdev); > + > + cache_coherency_ops_instance_unregister(&soc_hha->cci); > + iounmap(soc_hha->base); > + cache_coherency_ops_instance_put(&soc_hha->cci); > +} --Hs5fF3jxcDKPxATt Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCaPlPEAAKCRB4tDGHoIJi 0n5pAQCCL4y7CHzVqNXyyDfhRrqw9BjDlYs8MpqKde1NNQMUgwEAqS1sE14/IdwM Du1yl5LVFN+kra14elaLoO7/NifKDQg= =PAly -----END PGP SIGNATURE----- --Hs5fF3jxcDKPxATt--