[PATCH v5 0/3] AST2700 interrupt controller hierarchy support

[PATCH v5 0/3] AST2700 interrupt controller hierarchy support

[Ryan Chen]

This series introduces YAML bindings and driver support for the
ASPEED AST2700 interrupt controller hierarchy. The AST2700 SoC
contains two top-level interrupt controller blocks, INTC0 and
INTC1, each responsible for routing different interrupt groups
to various CPU targets.

v5:
- Adds two new YAML bindings:
 - aspeed,ast2700-intc0.yaml
 - aspeed,ast2700-intc1.yaml
- irq-aspeed-intc.c
 - add aspeed,ast2700-intc0-ic, aspeed,ast2700-intc0-ic compatible.

v4:
- aspeed,ast2700-intc.yaml
 - Clarify the relationship between INTC0/INTC1 parent nodes, the
   aspeed,ast2700-intc-ic child nodes, and the GIC.
 - Add a block diagram and DT examples showing the cascaded wiring
   (GIC <- INTC0 <- INTC1 children).
 - Mirrors the datasheet-described topology and register map, including
   the separation of INTC0/INTC1 regions.
 - Lets DT unambiguously express first-level (GIC parent) and cascaded
   second-level (INTC0 parent) interrupt controllers via examples that
   use `interrupts` for INTC0 children and `interrupts-extended` for
   INTC1 children routed into INTC0.

- irq-ast2700-intc.c
 - Drop all string decoding and human readable tables.
   Debugfs now dumps raw routing/protection registers only.
 - Split into a separate source file and made it modular
 - If the compatible not match ast2700-intc0/1, bail out return -ENODEV.

v3:
- aspeed,ast2700-intc.yaml
  - Clarify the relationship between INTC0/INTC1 parent nodes, the
    aspeed,ast2700-intc-ic child nodes, and the GIC.
  - Add a block diagram and DT examples showing the cascaded wiring
    (GIC <- INTC0 <- INTC1 children).
  - Mirrors the datasheet-described topology and register map, including
    the separation of INTC0/INTC1 regions and their routing/protection
    registers.
  - Lets DT unambiguously express first-level (GIC parent) and cascaded
    second-level (INTC0 parent) interrupt controllers via examples that
    use `interrupts` for INTC0 children and `interrupts-extended` for
    INTC1 children routed into INTC0.
  
- irq-aspeed-intc.c
  - separate c file from irq-aspeed-intc.c
  - make m

v2:
- fix dt bindingcheck

Ryan Chen (3):
  dt-bindings: interrupt-controller: aspeed,ast2700: Add support for
    INTC hierarchy
  Irqchip/ast2700-intc: add debugfs support for routing/protection
    display
  irqchip: aspeed: add compatible strings for ast2700-intc0-ic and
    ast2700-intc1-ic

 .../aspeed,ast2700-intc0.yaml                 |  97 ++++++++++
 .../aspeed,ast2700-intc1.yaml                 |  94 ++++++++++
 drivers/irqchip/Kconfig                       |   6 +
 drivers/irqchip/Makefile                      |   1 +
 drivers/irqchip/irq-aspeed-intc.c             |   2 +
 drivers/irqchip/irq-ast2700-intc.c            | 174 ++++++++++++++++++
 6 files changed, 374 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
 create mode 100644 drivers/irqchip/irq-ast2700-intc.c

-- 
2.34.1

[PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy

[Ryan Chen]

AST2700 contains two-level interrupt controllers (INTC0 and INTC1),
each with its own register space and handling different sets of
peripherals.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 .../aspeed,ast2700-intc0.yaml                 | 97 +++++++++++++++++++
 .../aspeed,ast2700-intc1.yaml                 | 94 ++++++++++++++++++
 2 files changed, 191 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
new file mode 100644
index 000000000000..93a5b142b0a2
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+maintainers:
+  - Ryan Chen <ryan_chen@aspeedtech.com>
+
+title: ASPEED AST2700 Interrupt Controller 0
+
+description:
+  This interrupt controller hardware is first level interrupt controller that
+  is hooked to the GIC interrupt controller. It's useful to combine multiple
+  interrupt sources into 1 interrupt to GIC interrupt controller.
+
+properties:
+  compatible:
+    const: aspeed,ast2700-intc0
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  ranges: true
+
+patternProperties:
+  "^interrupt-controller@":
+    type: object
+    description: A child interrupt controller node
+    additionalProperties: false
+
+    properties:
+      compatible:
+        enum:
+          - aspeed,ast2700-intc0-ic
+
+      reg:
+        maxItems: 1
+
+      '#interrupt-cells':
+        const: 1
+
+      interrupt-controller: true
+
+      interrupts:
+        minItems: 1
+        maxItems: 10
+
+    required:
+      - compatible
+      - reg
+      - interrupt-controller
+      - '#interrupt-cells'
+      - interrupts
+
+required:
+  - compatible
+  - reg
+  - '#address-cells'
+  - '#size-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    intc0: interrupt-controller@12100000 {
+        compatible = "aspeed,ast2700-intc0";
+        reg = <0x12100000 0x4000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0x0 0x12100000 0x4000>;
+
+        intc0_11: interrupt-controller@1b00 {
+            #interrupt-cells = <1>;
+            interrupt-controller;
+            compatible = "aspeed,ast2700-intc0-ic";
+            reg = <0x1b00 0x10>;
+            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
+        };
+    };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
new file mode 100644
index 000000000000..2f807d074211
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+maintainers:
+  - Ryan Chen <ryan_chen@aspeedtech.com>
+
+title: ASPEED AST2700 Interrupt Controller 1
+
+description:
+  This interrupt controller hardware is second level interrupt controller that
+  is hooked to a parent interrupt controller. It's useful to combine multiple
+  interrupt sources into 1 interrupt to parent interrupt controller.
+
+properties:
+  compatible:
+    const: aspeed,ast2700-intc1
+
+  reg:
+    maxItems: 1
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  ranges: true
+
+patternProperties:
+  "^interrupt-controller@":
+    type: object
+    description: A child interrupt controller node
+    additionalProperties: false
+
+    properties:
+      compatible:
+        enum:
+          - aspeed,ast2700-intc1-ic
+
+      reg:
+        maxItems: 1
+
+      '#interrupt-cells':
+        const: 1
+
+      interrupt-controller: true
+
+      interrupts-extended:
+        minItems: 1
+        maxItems: 1
+
+    required:
+      - compatible
+      - reg
+      - interrupt-controller
+      - '#interrupt-cells'
+      - interrupts-extended
+
+required:
+  - compatible
+  - reg
+  - '#address-cells'
+  - '#size-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    intc1: interrupt-controller@14c18000 {
+        compatible = "aspeed,ast2700-intc1";
+        reg = <0x14c18000 0x400>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0x0 0x14c18000 0x400>;
+
+        intc1_0: interrupt-controller@100 {
+            compatible = "aspeed,ast2700-intc1-ic";
+            reg = <0x100 0x10>;
+            #interrupt-cells = <1>;
+            interrupt-controller;
+            interrupts-extended = <&intc0_11 0>;
+        };
+
+        intc1_1: interrupt-controller@110 {
+            compatible = "aspeed,ast2700-intc1-ic";
+            reg = <0x110 0x10>;
+            #interrupt-cells = <1>;
+            interrupt-controller;
+            interrupts-extended = <&intc0_11 1>;
+        };
+    };
\ No newline at end of file
-- 
2.34.1

Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy

[Rob Herring (Arm)]

On Wed, 22 Oct 2025 14:55:05 +0800, Ryan Chen wrote:
> AST2700 contains two-level interrupt controllers (INTC0 and INTC1),
> each with its own register space and handling different sets of
> peripherals.
> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  .../aspeed,ast2700-intc0.yaml                 | 97 +++++++++++++++++++
>  .../aspeed,ast2700-intc1.yaml                 | 94 ++++++++++++++++++
>  2 files changed, 191 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:
./Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml:94:7: [error] no new line character at the end of file (new-line-at-end-of-file)
./Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml:97:7: [error] no new line character at the end of file (new-line-at-end-of-file)

dtschema/dtc warnings/errors:

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20251022065507.1152071-2-ryan_chen@aspeedtech.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy

[Rob Herring]

On Wed, Oct 22, 2025 at 02:55:05PM +0800, Ryan Chen wrote:
> AST2700 contains two-level interrupt controllers (INTC0 and INTC1),
> each with its own register space and handling different sets of
> peripherals.

This is a mess!

How does this relate to the existing "aspeed,ast2700-intc-ic"? Its 
schema has a block diagram of connections which I can understand. This 
does not.

The use of child nodes here is questionable. A variable number of 
interrupt banks is not a reason to have child nodes. I'm only guessing 
that's what's happening here because you haven't explained it.

> 
> Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> ---
>  .../aspeed,ast2700-intc0.yaml                 | 97 +++++++++++++++++++
>  .../aspeed,ast2700-intc1.yaml                 | 94 ++++++++++++++++++
>  2 files changed, 191 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
> new file mode 100644
> index 000000000000..93a5b142b0a2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc0.yaml
> @@ -0,0 +1,97 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc0.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +maintainers:
> +  - Ryan Chen <ryan_chen@aspeedtech.com>
> +
> +title: ASPEED AST2700 Interrupt Controller 0
> +
> +description:
> +  This interrupt controller hardware is first level interrupt controller that
> +  is hooked to the GIC interrupt controller. It's useful to combine multiple
> +  interrupt sources into 1 interrupt to GIC interrupt controller.
> +
> +properties:
> +  compatible:
> +    const: aspeed,ast2700-intc0
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^interrupt-controller@":
> +    type: object
> +    description: A child interrupt controller node
> +    additionalProperties: false
> +
> +    properties:
> +      compatible:
> +        enum:
> +          - aspeed,ast2700-intc0-ic
> +
> +      reg:
> +        maxItems: 1
> +
> +      '#interrupt-cells':
> +        const: 1
> +
> +      interrupt-controller: true
> +
> +      interrupts:
> +        minItems: 1
> +        maxItems: 10

What are the 10 different interrupts? You have to define what each one 
is.

> +
> +    required:
> +      - compatible
> +      - reg
> +      - interrupt-controller
> +      - '#interrupt-cells'
> +      - interrupts
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    intc0: interrupt-controller@12100000 {

This node is not an interrupt-controller.

> +        compatible = "aspeed,ast2700-intc0";
> +        reg = <0x12100000 0x4000>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges = <0x0 0x12100000 0x4000>;
> +
> +        intc0_11: interrupt-controller@1b00 {
> +            #interrupt-cells = <1>;
> +            interrupt-controller;
> +            compatible = "aspeed,ast2700-intc0-ic";
> +            reg = <0x1b00 0x10>;
> +            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
> +        };
> +    };
> \ No newline at end of file

Fix.

> diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> new file mode 100644
> index 000000000000..2f807d074211
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc1.yaml
> @@ -0,0 +1,94 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc1.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +maintainers:
> +  - Ryan Chen <ryan_chen@aspeedtech.com>
> +
> +title: ASPEED AST2700 Interrupt Controller 1
> +
> +description:
> +  This interrupt controller hardware is second level interrupt controller that
> +  is hooked to a parent interrupt controller. It's useful to combine multiple
> +  interrupt sources into 1 interrupt to parent interrupt controller.
> +
> +properties:
> +  compatible:
> +    const: aspeed,ast2700-intc1
> +
> +  reg:
> +    maxItems: 1
> +
> +  '#address-cells':
> +    const: 1
> +
> +  '#size-cells':
> +    const: 1
> +
> +  ranges: true
> +
> +patternProperties:
> +  "^interrupt-controller@":
> +    type: object
> +    description: A child interrupt controller node
> +    additionalProperties: false
> +
> +    properties:
> +      compatible:
> +        enum:
> +          - aspeed,ast2700-intc1-ic
> +
> +      reg:
> +        maxItems: 1
> +
> +      '#interrupt-cells':
> +        const: 1
> +
> +      interrupt-controller: true
> +
> +      interrupts-extended:
> +        minItems: 1
> +        maxItems: 1
> +
> +    required:
> +      - compatible
> +      - reg
> +      - interrupt-controller
> +      - '#interrupt-cells'
> +      - interrupts-extended
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#address-cells'
> +  - '#size-cells'
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    intc1: interrupt-controller@14c18000 {
> +        compatible = "aspeed,ast2700-intc1";
> +        reg = <0x14c18000 0x400>;
> +        #address-cells = <1>;
> +        #size-cells = <1>;
> +        ranges = <0x0 0x14c18000 0x400>;
> +
> +        intc1_0: interrupt-controller@100 {
> +            compatible = "aspeed,ast2700-intc1-ic";
> +            reg = <0x100 0x10>;
> +            #interrupt-cells = <1>;
> +            interrupt-controller;
> +            interrupts-extended = <&intc0_11 0>;
> +        };
> +
> +        intc1_1: interrupt-controller@110 {
> +            compatible = "aspeed,ast2700-intc1-ic";
> +            reg = <0x110 0x10>;
> +            #interrupt-cells = <1>;
> +            interrupt-controller;
> +            interrupts-extended = <&intc0_11 1>;
> +        };
> +    };
> \ No newline at end of file
> -- 
> 2.34.1
> 

RE: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy

[Ryan Chen]

Hello Rob.
	Thank you for your detailed review and comments.

> Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700:
> Add support for INTC hierarchy
> 
> On Wed, Oct 22, 2025 at 02:55:05PM +0800, Ryan Chen wrote:
> > AST2700 contains two-level interrupt controllers (INTC0 and INTC1),
> > each with its own register space and handling different sets of
> > peripherals.
> 
> This is a mess!
> 
> How does this relate to the existing "aspeed,ast2700-intc-ic"? Its schema has a
> block diagram of connections which I can understand. This does not.
> 
> The use of child nodes here is questionable. A variable number of interrupt
> banks is not a reason to have child nodes. I'm only guessing that's what's
> happening here because you haven't explained it.

Let me clarify the hardware structure and the purpose of these bindings.

The AST2700 SoC includes two top-level interrupt controller modules,
INTC0 and INTC1. (aspeed,ast2700-intc0, aspeed,ast2700-intc1)
Each of them provides routing selection and register protection
features.
Within each INTCx block, there are multiple sub-blocks called
intc-ic, each handling multi-interrupt sources.
("aspeed,ast2700-intc0-ic", "aspeed,ast2700-intc1-ic")

Cascading occurs between the child banks:
Level 1 : intc0-ic have multi-interrupts connect to GIC (root)
Level 2 : multi Intc1-ic# connect to intc0-ic
The parent intc0/1 nodes expose register regions for routing and
protection control, serving as containers for their intc-ic children.

The following simplified diagram shows the hierarchy:


                                 +----------+       +----------+
                                 |  intc0   |       |  intc1   |
- - - - - - - - - - - - - - - - -+---- -----+- -  - +------ - -+
  +-----------------------+      |          |       |          |
  | +-------+ +---------+ |      |          |       |          |
  | |       | |         | |      |          |       |          |
  | |  PSP  +-+ GIC     | |      |          |       |          |
  | |       | |         | |      |          |       |          |
  | +-------+ |         | |      |          |       |          |
  |           |         | |      +----------+       |          |
  |           | 192~201 <-|------+          <-------+ intc1-ic |
  |           +---------+ |      |          |       |          |
  +-----------------------+      | intc0-ic <-------+ intc1-ic |
                                 |          |       |          |
                                 | 			<-------+ intc1-ic |
                                 +----------+		  .....


> 
> >
> > Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
> > ---
> >  .../aspeed,ast2700-intc0.yaml                 | 97
> +++++++++++++++++++
> >  .../aspeed,ast2700-intc1.yaml                 | 94
> ++++++++++++++++++
> >  2 files changed, 191 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-
> > intc0.yaml  create mode 100644
> > Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-
> > intc1.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc0.yaml
> > b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc0.yaml
> > new file mode 100644
> > index 000000000000..93a5b142b0a2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,as
> > +++ t2700-intc0.yaml
> > @@ -0,0 +1,97 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int
> > +c0.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +maintainers:
> > +  - Ryan Chen <ryan_chen@aspeedtech.com>
> > +
> > +title: ASPEED AST2700 Interrupt Controller 0
> > +
> > +description:
> > +  This interrupt controller hardware is first level interrupt
> > +controller that
> > +  is hooked to the GIC interrupt controller. It's useful to combine
> > +multiple
> > +  interrupt sources into 1 interrupt to GIC interrupt controller.
> > +
> > +properties:
> > +  compatible:
> > +    const: aspeed,ast2700-intc0
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#address-cells':
> > +    const: 1
> > +
> > +  '#size-cells':
> > +    const: 1
> > +
> > +  ranges: true
> > +
> > +patternProperties:
> > +  "^interrupt-controller@":
> > +    type: object
> > +    description: A child interrupt controller node
> > +    additionalProperties: false
> > +
> > +    properties:
> > +      compatible:
> > +        enum:
> > +          - aspeed,ast2700-intc0-ic
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      '#interrupt-cells':
> > +        const: 1
> > +
> > +      interrupt-controller: true
> > +
> > +      interrupts:
> > +        minItems: 1
> > +        maxItems: 10
> 
> What are the 10 different interrupts? You have to define what each one is.
In currently design in level 1, intc0-ic connect 10 interrupts to CPU GIC. 
So, should i use const:10 or I just use minItems: 1?

> 
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - interrupt-controller
> > +      - '#interrupt-cells'
> > +      - interrupts
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#address-cells'
> > +  - '#size-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    intc0: interrupt-controller@12100000 {
> 
> This node is not an interrupt-controller.

If can't use the interrupt-controller here.
What can I use? "intc0: controller@12100000" is ok ??

> 
> > +        compatible = "aspeed,ast2700-intc0";
> > +        reg = <0x12100000 0x4000>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        ranges = <0x0 0x12100000 0x4000>;
> > +
> > +        intc0_11: interrupt-controller@1b00 {
> > +            #interrupt-cells = <1>;
> > +            interrupt-controller;
> > +            compatible = "aspeed,ast2700-intc0-ic";
> > +            reg = <0x1b00 0x10>;
> > +            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> > +                         <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
> > +        };
> > +    };
> > \ No newline at end of file
> 
> Fix.

Will fix it in next version.

> 
> > diff --git
> > a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc1.yaml
> > b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast270
> > 0-intc1.yaml
> > new file mode 100644
> > index 000000000000..2f807d074211
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,as
> > +++ t2700-intc1.yaml
> > @@ -0,0 +1,94 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-int
> > +c1.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +maintainers:
> > +  - Ryan Chen <ryan_chen@aspeedtech.com>
> > +
> > +title: ASPEED AST2700 Interrupt Controller 1
> > +
> > +description:
> > +  This interrupt controller hardware is second level interrupt
> > +controller that
> > +  is hooked to a parent interrupt controller. It's useful to combine
> > +multiple
> > +  interrupt sources into 1 interrupt to parent interrupt controller.
> > +
> > +properties:
> > +  compatible:
> > +    const: aspeed,ast2700-intc1
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  '#address-cells':
> > +    const: 1
> > +
> > +  '#size-cells':
> > +    const: 1
> > +
> > +  ranges: true
> > +
> > +patternProperties:
> > +  "^interrupt-controller@":
> > +    type: object
> > +    description: A child interrupt controller node
> > +    additionalProperties: false
> > +
> > +    properties:
> > +      compatible:
> > +        enum:
> > +          - aspeed,ast2700-intc1-ic
> > +
> > +      reg:
> > +        maxItems: 1
> > +
> > +      '#interrupt-cells':
> > +        const: 1
> > +
> > +      interrupt-controller: true
> > +
> > +      interrupts-extended:
> > +        minItems: 1
> > +        maxItems: 1
> > +
> > +    required:
> > +      - compatible
> > +      - reg
> > +      - interrupt-controller
> > +      - '#interrupt-cells'
> > +      - interrupts-extended
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - '#address-cells'
> > +  - '#size-cells'
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    intc1: interrupt-controller@14c18000 {
> > +        compatible = "aspeed,ast2700-intc1";
> > +        reg = <0x14c18000 0x400>;
> > +        #address-cells = <1>;
> > +        #size-cells = <1>;
> > +        ranges = <0x0 0x14c18000 0x400>;
> > +
> > +        intc1_0: interrupt-controller@100 {
> > +            compatible = "aspeed,ast2700-intc1-ic";
> > +            reg = <0x100 0x10>;
> > +            #interrupt-cells = <1>;
> > +            interrupt-controller;
> > +            interrupts-extended = <&intc0_11 0>;
> > +        };
> > +
> > +        intc1_1: interrupt-controller@110 {
> > +            compatible = "aspeed,ast2700-intc1-ic";
> > +            reg = <0x110 0x10>;
> > +            #interrupt-cells = <1>;
> > +            interrupt-controller;
> > +            interrupts-extended = <&intc0_11 1>;
> > +        };
> > +    };
> > \ No newline at end of file
> > --
> > 2.34.1
> >

Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy

[Rob Herring]

On Thu, Oct 23, 2025 at 06:57:01AM +0000, Ryan Chen wrote:
> Hello Rob.
> 	Thank you for your detailed review and comments.
> 
> > Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700:
> > Add support for INTC hierarchy
> > 
> > On Wed, Oct 22, 2025 at 02:55:05PM +0800, Ryan Chen wrote:
> > > AST2700 contains two-level interrupt controllers (INTC0 and INTC1),
> > > each with its own register space and handling different sets of
> > > peripherals.
> > 
> > This is a mess!
> > 
> > How does this relate to the existing "aspeed,ast2700-intc-ic"? Its schema has a
> > block diagram of connections which I can understand. This does not.
> > 
> > The use of child nodes here is questionable. A variable number of interrupt
> > banks is not a reason to have child nodes. I'm only guessing that's what's
> > happening here because you haven't explained it.
> 
> Let me clarify the hardware structure and the purpose of these bindings.
> 
> The AST2700 SoC includes two top-level interrupt controller modules,
> INTC0 and INTC1. (aspeed,ast2700-intc0, aspeed,ast2700-intc1)
> Each of them provides routing selection and register protection
> features.
> Within each INTCx block, there are multiple sub-blocks called
> intc-ic, each handling multi-interrupt sources.
> ("aspeed,ast2700-intc0-ic", "aspeed,ast2700-intc1-ic")
> 
> Cascading occurs between the child banks:
> Level 1 : intc0-ic have multi-interrupts connect to GIC (root)
> Level 2 : multi Intc1-ic# connect to intc0-ic
> The parent intc0/1 nodes expose register regions for routing and
> protection control, serving as containers for their intc-ic children.

Being a 2nd vs. 3rd level interrupt controller is not a reason for 
different compatibles. The programming model is obviously the same for 
both as you essentially have 0 driver changes. Having N banks of 32 
interrupts vs. 1 bank of 32 interrupts is not a reason to have multiple 
intcN-ic nodes. That is a very common difference between instances of 
the same interrupt controller such as the GIC.

What you need to do is simply extend your driver to support N banks of 
32 interrupts. That's what almost every other irqchip driver with more 
than 32 interrupts does. If you are lucky, then the offset to each 
bank's registers is just hwirq/32 * <bank stride> and the number of 
banks can be calculated from the length of 'reg'. If you are not 
lucky, then you could put 1 'reg' entry for each bank.

AFAICT, the existing binding in aspeed,ast2700-intc.yaml should work for 
you.

> 
> The following simplified diagram shows the hierarchy:
> 
> 
>                                  +----------+       +----------+
>                                  |  intc0   |       |  intc1   |
> - - - - - - - - - - - - - - - - -+---- -----+- -  - +------ - -+
>   +-----------------------+      |          |       |          |
>   | +-------+ +---------+ |      |          |       |          |
>   | |       | |         | |      |          |       |          |
>   | |  PSP  +-+ GIC     | |      |          |       |          |
>   | |       | |         | |      |          |       |          |
>   | +-------+ |         | |      |          |       |          |
>   |           |         | |      +----------+       |          |
>   |           | 192~201 <-|------+          <-------+ intc1-ic |
>   |           +---------+ |      |          |       |          |
>   +-----------------------+      | intc0-ic <-------+ intc1-ic |
>                                  |          |       |          |
>                                  | 			<-------+ intc1-ic |
>                                  +----------+		  .....

You already match on intc0 and handle 32 interrupts. Now you are adding 
intc0-ic to match on and handling the same 32 interrupts?

Rob

RE: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700: Add support for INTC hierarchy

[Ryan Chen]

> Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller: aspeed,ast2700:
> Add support for INTC hierarchy
> 
> On Thu, Oct 23, 2025 at 06:57:01AM +0000, Ryan Chen wrote:
> > Hello Rob.
> > 	Thank you for your detailed review and comments.
> >
> > > Subject: Re: [PATCH v5 1/3] dt-bindings: interrupt-controller:
> aspeed,ast2700:
> > > Add support for INTC hierarchy
> > >
> > > On Wed, Oct 22, 2025 at 02:55:05PM +0800, Ryan Chen wrote:
> > > > AST2700 contains two-level interrupt controllers (INTC0 and
> > > > INTC1), each with its own register space and handling different
> > > > sets of peripherals.
> > >
> > > This is a mess!
> > >
> > > How does this relate to the existing "aspeed,ast2700-intc-ic"? Its
> > > schema has a block diagram of connections which I can understand. This
> does not.
> > >
> > > The use of child nodes here is questionable. A variable number of
> > > interrupt banks is not a reason to have child nodes. I'm only
> > > guessing that's what's happening here because you haven't explained it.
> >
> > Let me clarify the hardware structure and the purpose of these bindings.
> >
> > The AST2700 SoC includes two top-level interrupt controller modules,
> > INTC0 and INTC1. (aspeed,ast2700-intc0, aspeed,ast2700-intc1) Each of
> > them provides routing selection and register protection features.
> > Within each INTCx block, there are multiple sub-blocks called intc-ic,
> > each handling multi-interrupt sources.
> > ("aspeed,ast2700-intc0-ic", "aspeed,ast2700-intc1-ic")
> >
> > Cascading occurs between the child banks:
> > Level 1 : intc0-ic have multi-interrupts connect to GIC (root) Level 2
> > : multi Intc1-ic# connect to intc0-ic The parent intc0/1 nodes expose
> > register regions for routing and protection control, serving as
> > containers for their intc-ic children.
> 
> Being a 2nd vs. 3rd level interrupt controller is not a reason for different
> compatibles. The programming model is obviously the same for both as you
> essentially have 0 driver changes. Having N banks of 32 interrupts vs. 1 bank of
> 32 interrupts is not a reason to have multiple intcN-ic nodes. That is a very
> common difference between instances of the same interrupt controller such as
> the GIC.
> 
> What you need to do is simply extend your driver to support N banks of
> 32 interrupts. That's what almost every other irqchip driver with more than 32
> interrupts does. If you are lucky, then the offset to each bank's registers is just
> hwirq/32 * <bank stride> and the number of banks can be calculated from the
> length of 'reg'. If you are not lucky, then you could put 1 'reg' entry for each
> bank.
> 
> AFAICT, the existing binding in aspeed,ast2700-intc.yaml should work for you.
> 
> >
> > The following simplified diagram shows the hierarchy:
> >
> >
> >                                  +----------+       +----------+
> >                                  |  intc0   |       |  intc1   |
> > - - - - - - - - - - - - - - - - -+---- -----+- -  - +------ - -+
> >   +-----------------------+      |          |       |          |
> >   | +-------+ +---------+ |      |          |       |          |
> >   | |       | |         | |      |          |       |          |
> >   | |  PSP  +-+ GIC     | |      |          |       |          |
> >   | |       | |         | |      |          |       |          |
> >   | +-------+ |         | |      |          |       |          |
> >   |           |         | |      +----------+       |          |
> >   |           | 192~201 <-|------+          <-------+ intc1-ic |
> >   |           +---------+ |      |          |       |          |
> >   +-----------------------+      | intc0-ic <-------+ intc1-ic |
> >                                  |          |       |
> |
> >                                  | 			<-------+ intc1-ic |
> >                                  +----------+		  .....
> 
> You already match on intc0 and handle 32 interrupts. Now you are adding
> intc0-ic to match on and handling the same 32 interrupts?

Thank your guidance, understood your point. the currently is met requirement.
For currently aspeed,ast2700-intc.yaml I still need update following.
#1. Interrupts:
	- maxItems: 6
    + minItems: 1
    + maxItems: 10

The 1 level request multi-interrupt to root GIC, the max is 10.
2nd level only request 1 to level 1 intc-ic. 
in level 1: will be need 10, 2nd level only need 1.
	
Level1 : 
        intc0_11: interrupt-controller@12101b00 {
            compatible = "aspeed,ast2700-intc-ic";
            reg = <0x0 0x12101b00 0x0 0x10>;
            #interrupt-cells = <1>;
            interrupt-controller;
            interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
                    <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
        };

Level 2:
     intc1_0: interrupt-controller@14c18100 {
            compatible = "aspeed,ast2700-intc-ic";
            reg = <0x0 0x14c18100 0x0 0x10>;
            #interrupt-cells = <1>;
            interrupt-controller;
            interrupts-extended = <&intc0_11 0>;
        };

#2. '#interrupt-cells':
    -const: 2 
    +const: 1
Due to the driver irq-aspeed-intc.c not support any trigger type. 


> 
> Rob

[PATCH v5 2/3] Irqchip/ast2700-intc: add debugfs support for routing/protection display

[Ryan Chen]

AST2700 INTC0/INTC1 nodes ("aspeed,ast2700-intc0/1") not only
include the interrupt controller child node ("aspeed,ast2700-intc-ic"),
but also provide interrupt routing and register protection features.
Adds debugfs entries for interrupt routing and protection status for
AST2700 INTC0/INTC1.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 drivers/irqchip/Kconfig            |   6 +
 drivers/irqchip/Makefile           |   1 +
 drivers/irqchip/irq-ast2700-intc.c | 174 +++++++++++++++++++++++++++++
 3 files changed, 181 insertions(+)
 create mode 100644 drivers/irqchip/irq-ast2700-intc.c

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index a61c6dc63c29..75922d5c4da6 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -111,6 +111,12 @@ config AL_FIC
 	help
 	  Support Amazon's Annapurna Labs Fabric Interrupt Controller.
 
+config AST2700_INTC
+	tristate "AST2700 Interrupt Controller"
+	depends on ARCH_ASPEED
+	help
+	  Support AST2700 Interrupt Controller.
+
 config ATMEL_AIC_IRQ
 	bool
 	select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 3de083f5484c..055724a9e536 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_LS_EXTIRQ)			+= irq-ls-extirq.o
 obj-$(CONFIG_LS_SCFG_MSI)		+= irq-ls-scfg-msi.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-vic.o irq-aspeed-i2c-ic.o irq-aspeed-scu-ic.o
 obj-$(CONFIG_ARCH_ASPEED)		+= irq-aspeed-intc.o
+obj-$(CONFIG_AST2700_INTC)		+= irq-ast2700-intc.o
 obj-$(CONFIG_STM32MP_EXTI)		+= irq-stm32mp-exti.o
 obj-$(CONFIG_STM32_EXTI) 		+= irq-stm32-exti.o
 obj-$(CONFIG_QCOM_IRQ_COMBINER)		+= qcom-irq-combiner.o
diff --git a/drivers/irqchip/irq-ast2700-intc.c b/drivers/irqchip/irq-ast2700-intc.c
new file mode 100644
index 000000000000..7c7241539fe5
--- /dev/null
+++ b/drivers/irqchip/irq-ast2700-intc.c
@@ -0,0 +1,174 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * AST2700 Interrupt Controller
+ */
+
+#include <linux/debugfs.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/seq_file.h>
+
+/* INTC0 register layout */
+#define INTC0_PROT_OFFS           0x40
+#define INTC0_ROUTING_SEL0_BASE   0x200
+#define INTC0_ROUTING_GAP         0x100
+#define INTC0_GROUPS              4
+
+/* INTC1 register layout */
+#define INTC1_PROT_OFFS           0x00
+#define INTC1_ROUTING_SEL0_BASE   0x80
+#define INTC1_ROUTING_GAP         0x20
+#define INTC1_GROUPS              6
+
+struct aspeed_intc_data {
+	const char                  *name;
+	u32                          prot_offs;
+	u32                          rout_sel0_base;
+	u32                          rout_gap;
+	unsigned int                 groups;
+};
+
+static const struct aspeed_intc_data aspeed_intc0_data = {
+	.name            = "INTC0",
+	.prot_offs       = INTC0_PROT_OFFS,
+	.rout_sel0_base  = INTC0_ROUTING_SEL0_BASE,
+	.rout_gap        = INTC0_ROUTING_GAP,
+	.groups          = INTC0_GROUPS,
+};
+
+static const struct aspeed_intc_data aspeed_intc1_data = {
+	.name            = "INTC1",
+	.prot_offs       = INTC1_PROT_OFFS,
+	.rout_sel0_base  = INTC1_ROUTING_SEL0_BASE,
+	.rout_gap        = INTC1_ROUTING_GAP,
+	.groups          = INTC1_GROUPS,
+};
+
+struct aspeed_intc {
+	void __iomem                    *base;
+	const struct aspeed_intc_data   *data;
+#ifdef CONFIG_DEBUG_FS
+	struct dentry                   *dbg_root;
+#endif
+};
+
+#ifdef CONFIG_DEBUG_FS
+static int aspeed_intc_regs_show(struct seq_file *s, void *unused)
+{
+	struct aspeed_intc *intc = s->private;
+	const struct aspeed_intc_data *d = intc->data;
+	void __iomem *base = intc->base;
+	unsigned int i;
+
+	for (i = 0; i < d->groups; i++) {
+		void __iomem *b = base + d->rout_sel0_base + i * 4;
+		u32 r0 = readl(b);
+		u32 r1 = readl(b + d->rout_gap);
+		u32 r2 = readl(b + 2 * d->rout_gap);
+
+		seq_printf(s, "ROUTE[%u]: 0x%08x 0x%08x 0x%08x\n", i, r0, r1, r2);
+	}
+	return 0;
+}
+
+static int aspeed_intc_regs_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, aspeed_intc_regs_show, inode->i_private);
+}
+
+static const struct file_operations aspeed_intc_regs_fops = {
+	.owner    = THIS_MODULE,
+	.open     = aspeed_intc_regs_open,
+	.read     = seq_read,
+	.llseek   = seq_lseek,
+	.release  = single_release,
+};
+
+static int aspeed_intc_prot_show(struct seq_file *s, void *unused)
+{
+	struct aspeed_intc *intc = s->private;
+	const struct aspeed_intc_data *d = intc->data;
+	u32 prot = readl(intc->base + d->prot_offs);
+
+	seq_printf(s, "%s_PROT: 0x%08x\n", d->name, prot);
+	return 0;
+}
+
+static int aspeed_intc_prot_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, aspeed_intc_prot_show, inode->i_private);
+}
+
+static const struct file_operations aspeed_intc_prot_fops = {
+	.owner    = THIS_MODULE,
+	.open     = aspeed_intc_prot_open,
+	.read     = seq_read,
+	.llseek   = seq_lseek,
+	.release  = single_release,
+};
+#endif /* CONFIG_DEBUG_FS */
+
+static int aspeed_intc_probe(struct platform_device *pdev)
+{
+	const struct aspeed_intc_data *data;
+	struct aspeed_intc *intc;
+	struct resource *res;
+
+	data = of_device_get_match_data(&pdev->dev);
+	if (!data)
+		return -ENODEV;
+
+	intc = devm_kzalloc(&pdev->dev, sizeof(*intc), GFP_KERNEL);
+	if (!intc)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	intc->base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(intc->base))
+		return PTR_ERR(intc->base);
+
+	intc->data = data;
+
+	platform_set_drvdata(pdev, intc);
+
+#ifdef CONFIG_DEBUG_FS
+	intc->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), NULL);
+	if (intc->dbg_root) {
+		debugfs_create_file("routing", 0400, intc->dbg_root, intc,
+				    &aspeed_intc_regs_fops);
+		debugfs_create_file("protection", 0400, intc->dbg_root, intc,
+				    &aspeed_intc_prot_fops);
+	}
+#endif
+	return 0;
+}
+
+static void aspeed_intc_remove(struct platform_device *pdev)
+{
+#ifdef CONFIG_DEBUG_FS
+	struct aspeed_intc *intc = platform_get_drvdata(pdev);
+
+	if (intc && intc->dbg_root)
+		debugfs_remove_recursive(intc->dbg_root);
+#endif
+}
+
+static const struct of_device_id aspeed_intc_of_match[] = {
+	{ .compatible = "aspeed,ast2700-intc0", .data = &aspeed_intc0_data },
+	{ .compatible = "aspeed,ast2700-intc1", .data = &aspeed_intc1_data },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, aspeed_intc_of_match);
+
+static struct platform_driver aspeed_intc_driver = {
+	.probe   = aspeed_intc_probe,
+	.remove  = aspeed_intc_remove,
+	.driver  = {
+		.name           = "aspeed-ast2700-intc",
+		.of_match_table = aspeed_intc_of_match,
+	},
+};
+module_platform_driver(aspeed_intc_driver);
-- 
2.34.1

Re: [PATCH v5 2/3] Irqchip/ast2700-intc: add debugfs support for routing/protection display

[Thomas Gleixner]

On Wed, Oct 22 2025 at 14:55, Ryan Chen wrote:

The prefix is: irqchip/ast....:

> AST2700 INTC0/INTC1 nodes ("aspeed,ast2700-intc0/1") not only
> include the interrupt controller child node ("aspeed,ast2700-intc-ic"),
> but also provide interrupt routing and register protection features.

Lacks a new line to open a new paragraph.

> Adds debugfs entries for interrupt routing and protection status for

Add

> AST2700 INTC0/INTC1.

But what you are failing to explain is why this is required and
useful. Just adding code because we can is not a real good reason.

Thanks,

        tglx

RE: [PATCH v5 2/3] Irqchip/ast2700-intc: add debugfs support for routing/protection display

[Ryan Chen]

> Subject: Re: [PATCH v5 2/3] Irqchip/ast2700-intc: add debugfs support for
> routing/protection display
> 
> On Wed, Oct 22 2025 at 14:55, Ryan Chen wrote:
> 
> The prefix is: irqchip/ast....:

I'll use irqchip/aspeed-intc:

> 
> > AST2700 INTC0/INTC1 nodes ("aspeed,ast2700-intc0/1") not only include
> > the interrupt controller child node ("aspeed,ast2700-intc-ic"), but
> > also provide interrupt routing and register protection features.
> 
> Lacks a new line to open a new paragraph.

I'll split the opening sentence and the follow-up paragraph in
the commit message.
> 
> > Adds debugfs entries for interrupt routing and protection status for
> 
> Add

Will update

> 
> > AST2700 INTC0/INTC1.
> 
> But what you are failing to explain is why this is required and useful. Just
> adding code because we can is not a real good reason.

The INTC0/INTC1 routing and protection registers are set up by early firmware
and are not modified by Linux. 

When routing is off, interrupts get merged/misdirected silently.
A minimal kernel-side visibility helps confirm that the upstream interrupt
topology (e.g., which INTC1 groups are funneled to which INTC0 inputs / GIC SPIs)
matches what the DT and drivers assume.

The protection bits gate which CPU can write/read specific INTC 
windows (PSP/SSP/TSP). When those are mis-programmed, 
Linux can neither steer nor even read status in places it expects to. 
A raw readout lets us verify that Linux isn't boxed out by mistake.
> 
> Thanks,
> 
>         tglx

[PATCH v5 3/3] irqchip: aspeed: add compatible strings for ast2700-intc0-ic and ast2700-intc1-ic

[Ryan Chen]

The AST2700 SoC defines two parent interrupt controller blocks
(INTC0 and INTC1), each containing multiple interrupt-controller
child instances ("*-intc-ic"). The existing irqchip driver
(irq-aspeed-intc.c) currently only registers a single compatible
string: "aspeed,ast2700-intc-ic"

To support device trees that describe the INTC0 and INTC1
hierarchy more precisely, this patch adds two additional
compatible strings:
 - "aspeed,ast2700-intc0-ic"
 - "aspeed,ast2700-intc1-ic"

Both map to the same initialization function
`aspeed_intc_ic_of_init()`.

This allows DTS bindings and drivers for AST2700 INTC0/INTC1
to be matched correctly, while maintaining backward compatibility
with the original compatible string.

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
---
 drivers/irqchip/irq-aspeed-intc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/irqchip/irq-aspeed-intc.c b/drivers/irqchip/irq-aspeed-intc.c
index 8330221799a0..a40b406dc8fa 100644
--- a/drivers/irqchip/irq-aspeed-intc.c
+++ b/drivers/irqchip/irq-aspeed-intc.c
@@ -137,3 +137,5 @@ static int __init aspeed_intc_ic_of_init(struct device_node *node,
 }
 
 IRQCHIP_DECLARE(ast2700_intc_ic, "aspeed,ast2700-intc-ic", aspeed_intc_ic_of_init);
+IRQCHIP_DECLARE(ast2700_intc0_ic, "aspeed,ast2700-intc0-ic", aspeed_intc_ic_of_init);
+IRQCHIP_DECLARE(ast2700_intc1_ic, "aspeed,ast2700-intc1-ic", aspeed_intc_ic_of_init);
-- 
2.34.1

Re: [PATCH v5 3/3] irqchip: aspeed: add compatible strings for ast2700-intc0-ic and ast2700-intc1-ic

[Thomas Gleixner]

On Wed, Oct 22 2025 at 14:55, Ryan Chen wrote:

The subject prefix is: irqchip/aspeed-intc:

It's documented how to make them:

   https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#patch-subject

> The AST2700 SoC defines two parent interrupt controller blocks
> (INTC0 and INTC1), each containing multiple interrupt-controller
> child instances ("*-intc-ic"). The existing irqchip driver
> (irq-aspeed-intc.c) currently only registers a single compatible
> string: "aspeed,ast2700-intc-ic"
>
> To support device trees that describe the INTC0 and INTC1
> hierarchy more precisely, this patch adds two additional

s/this patch adds/add/

git grep 'This patch' Documentation/process/

> compatible strings:
>  - "aspeed,ast2700-intc0-ic"
>  - "aspeed,ast2700-intc1-ic"
>
> Both map to the same initialization function
> `aspeed_intc_ic_of_init()`.

The backticks are pointless. Just write aspeed...init()

Thanks,

        tglx

RE: [PATCH v5 3/3] irqchip: aspeed: add compatible strings for ast2700-intc0-ic and ast2700-intc1-ic

[Ryan Chen]

> Subject: Re: [PATCH v5 3/3] irqchip: aspeed: add compatible strings for
> ast2700-intc0-ic and ast2700-intc1-ic
> 
> On Wed, Oct 22 2025 at 14:55, Ryan Chen wrote:
> 
> The subject prefix is: irqchip/aspeed-intc:
> 
> It's documented how to make them:
> 
> 
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#patch-su
> bject

Thanks, will fix.
> 
> > The AST2700 SoC defines two parent interrupt controller blocks
> > (INTC0 and INTC1), each containing multiple interrupt-controller child
> > instances ("*-intc-ic"). The existing irqchip driver
> > (irq-aspeed-intc.c) currently only registers a single compatible
> > string: "aspeed,ast2700-intc-ic"
> >
> > To support device trees that describe the INTC0 and INTC1 hierarchy
> > more precisely, this patch adds two additional
> 
> s/this patch adds/add/
will fix.
> 
> git grep 'This patch' Documentation/process/
> 
will fix.

> > compatible strings:
> >  - "aspeed,ast2700-intc0-ic"
> >  - "aspeed,ast2700-intc1-ic"
> >
> > Both map to the same initialization function
> > `aspeed_intc_ic_of_init()`.
> 
> The backticks are pointless. Just write aspeed...init()

will fix.

Thanks a lot.
> 
> Thanks,
> 
>         tglx