From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB53ECCF9EB for ; Mon, 27 Oct 2025 08:42:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Nyf0iPPBKDUCm1JJTxpGpyrJI5JD1xYQCtOy3H1gw1s=; b=sK4bs4aAOgl/kfIBMXiExLvZ1D 7DHuOAjybmIDjk3M2LAYF6Us2k07/20MyrcVIXyA0pBBX68umWduidXqlX5NEmQsoOyYNdm3RLV+F /f6A+Nm3PtYp0pZE1I40oPiqZF1Qa4dYrAtq1wr/b/zlp5hSpNRhdaVy0ndd+8D0XHBzhp4mmBLxM EaooFeGbmvg8KB576OTU/xh9z69qOT2t0zmTSOTJrTLGOevWgd2VpqtbApFNVqAqwtGiHbtbG8fGe vIL+Sr1UvZab4r77APXjrAsFsue2LUlSinvwr0QHXINECk5FBdabpoYmZjMqlgq81Z0YrO/aORfFk OfY8Hxiw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vDInu-0000000DMcr-1iIN; Mon, 27 Oct 2025 08:42:14 +0000 Received: from mail-m49220.qiye.163.com ([45.254.49.220]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vDInh-0000000DMT8-2mG8; Mon, 27 Oct 2025 08:42:04 +0000 Received: from rockchip.. (unknown [58.22.7.114]) by smtp.qiye.163.com (Hmail) with ESMTP id 27504fff2; Mon, 27 Oct 2025 16:41:56 +0800 (GMT+08:00) From: Elaine Zhang To: mturquette@baylibre.com, sboyd@kernel.org, sugar.zhang@rock-chips.com, zhangqing@rock-chips.com, heiko@sntech.de, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, huangtao@rock-chips.com, finley.xiao@rock-chips.com Subject: [PATCH v5 4/7] dt-bindings: clock: Add support for rockchip pvtpll Date: Mon, 27 Oct 2025 16:41:44 +0800 Message-Id: <20251027084147.4148739-5-zhangqing@rock-chips.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251027084147.4148739-1-zhangqing@rock-chips.com> References: <20251027084147.4148739-1-zhangqing@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-HM-Tid: 0a9a24d4c84003a3kunmca0e4b6150f610 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFDSUNOT01LS0k3V1ktWUFJV1kPCRoVCBIfWUFZQ0lISVZDSUMdHRpIT0lNQxlWFRQJFh oXVRMBExYaEhckFA4PWVdZGBILWUFZTkNVSUlVTFVKSk9ZV1kWGg8SFR0UWUFZT0tIVUpLSEpKQk 1VSktLVUpCWQY+ DKIM-Signature: a=rsa-sha256; b=Hm5vlok8Iqe3qYyZjpbkIphk7T1bzgPkH6zQm/qiGPY8KNaaHmxJ72bfcJbKagYq1i8pCaKQiggRxN8amD6H/HyUEys1yZOcFuNNgF2hNxzuBAM7nHXkXQ5Grk02yyzn54uSeqx6Y51MIApT8+tYRAgXtiTeFLt6qS/PWFl/Hrg=; c=relaxed/relaxed; s=default; d=rock-chips.com; v=1; bh=Nyf0iPPBKDUCm1JJTxpGpyrJI5JD1xYQCtOy3H1gw1s=; h=date:mime-version:subject:message-id:from; X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251027_014201_876777_3FCABC20 X-CRM114-Status: GOOD ( 11.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add pvtpll documentation for rockchip. Signed-off-by: Elaine Zhang --- .../bindings/clock/rockchip,pvtpll.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,pvtpll.yaml diff --git a/Documentation/devicetree/bindings/clock/rockchip,pvtpll.yaml b/Documentation/devicetree/bindings/clock/rockchip,pvtpll.yaml new file mode 100644 index 000000000000..681024749d65 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/rockchip,pvtpll.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/rockchip,pvtpll.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip Pvtpll + +maintainers: + - Elaine Zhang + - Heiko Stuebner + +properties: + compatible: + enum: + - rockchip,rv1103b-core-pvtpll + - rockchip,rv1103b-enc-pvtpll + - rockchip,rv1103b-isp-pvtpll + - rockchip,rv1103b-npu-pvtpll + - rockchip,rv1126b-core-pvtpll + - rockchip,rv1126b-isp-pvtpll + - rockchip,rv1126b-enc-pvtpll + - rockchip,rv1126b-aisp-pvtpll + - rockchip,rv1126b-npu-pvtpll + - rockchip,rk3506-core-pvtpll + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + + clocks: + maxItems: 1 + + clock-output-names: + maxItems: 1 + + rockchip,cru: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Phandle to the main Clock and Reset Unit (CRU) controller. + Required for PVTPLLs that need to interact with the main CRU + for clock management operations. + +required: + - compatible + - reg + - "#clock-cells" + - clock-output-names + +additionalProperties: false + +examples: + - | + pvtpll@20480000 { + compatible = "rockchip,rv1126b-core-pvtpll"; + reg = <0x20480000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_core_pvtpll"; + }; + + - | + pvtpll@21c60000 { + compatible = "rockchip,rv1126b-isp-pvtpll"; + reg = <0x21c60000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_isp_pvtpll"; + rockchip,cru = <&cru>; + }; + + - | + pvtpll@21f00000 { + compatible = "rockchip,rv1126b-enc-pvtpll"; + reg = <0x21f00000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_vepu_pvtpll"; + }; + + - | + pvtpll@21fc0000 { + compatible = "rockchip,rv1126b-aisp-pvtpll"; + reg = <0x21fc0000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_vcp_pvtpll"; + rockchip,cru = <&cru>; + }; + + - | + pvtpll@22080000 { + compatible = "rockchip,rv1126b-npu-pvtpll"; + reg = <0x22080000 0x100>; + #clock-cells = <0>; + clock-output-names = "clk_npu_pvtpll"; + rockchip,cru = <&cru>; + }; + +... -- 2.34.1