[PATCH v2 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32

Jun Guo
2025-10-27T08:43:08Z

The Cadence SPI IP supports configurable FIFO data widths during
integration. On some SoCs, the FIFO data width is designed to be 16 or
32 bits at the chip design stage. However, the current driver only
supports communication with an 8-bit FIFO data width. Therefore, these
patches are added to enable the driver to support communication with
16-bit and 32-bit FIFO data widths.

This series introduces the following enhancements for Cadence SPI
controller support on arm64 platforms:

Patch 1: Add a compatible string "cix,sky1-spi-r1p6" for the cix
sky1 SoC.
Patch 2: Update DT binding docs to support cix sky1 SoC.
Patch 3: Enhance the SPI Cadence driver to support data transmission
with bits_per_word values of 16 and 32.

The CIX Sky1 SPI supported patch is added:
https://lore.kernel.org/all/20250919013118.853078-1-jun.guo@cixtech.com/

The patches have been tested on CIX SKY1 platform.

Changes for v2:
- Remove the fifo-width property and add a compatible string for the
cix sky1 SoC to control the FIFO data width configuration.

Jun Guo (3):
arm64: dts: cix: add a compatible string for the cix sky1 SoC
dt-bindings: spi: spi-cadence: update DT binding docs to support cix
sky1 SoC
spi: spi-cadence: supports transmission with bits_per_word of 16 and
32

.../devicetree/bindings/spi/spi-cadence.yaml | 11 +-
arch/arm64/boot/dts/cix/sky1.dtsi | 4 +-
drivers/spi/spi-cadence.c | 106 +++++++++++++++---
3 files changed, 103 insertions(+), 18 deletions(-)

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2.34.1