From: Peter Griffin <peter.griffin@linaro.org>
To: "Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Alim Akhtar" <alim.akhtar@samsung.com>,
"André Draszik" <andre.draszik@linaro.org>,
"Tudor Ambarus" <tudor.ambarus@linaro.org>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Sam Protsenko" <semen.protsenko@linaro.org>,
"Sylwester Nawrocki" <s.nawrocki@samsung.com>,
"Chanwoo Choi" <cw00.choi@samsung.com>
Cc: Will McVicker <willmcvicker@google.com>,
Krzysztof Kozlowski <krzk@kernel.org>,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org, kernel-team@android.com,
Peter Griffin <peter.griffin@linaro.org>,
Krzysztof Kozlowski <krzk@kernel.org>
Subject: [PATCH v2 2/4] arm64: dts: exynos: gs101: add samsung,sysreg property to CMU nodes
Date: Wed, 29 Oct 2025 21:29:23 +0000 [thread overview]
Message-ID: <20251029-automatic-clocks-v2-2-f8edd3a2d82b@linaro.org> (raw)
In-Reply-To: <20251029-automatic-clocks-v2-0-f8edd3a2d82b@linaro.org>
sysreg bank contains BUSCOMPONENT_DRCG_EN and MEMCLK clock registers that
need to be initialized in the CMU clock driver.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
arch/arm64/boot/dts/exynos/google/gs101.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index d06d1d05f36408137a8acd98e43d48ea7d4f4292..c39ca4c4508f046ca16ae86be42468c7245561b8 100644
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -578,6 +578,7 @@ cmu_misc: clock-controller@10010000 {
clocks = <&cmu_top CLK_DOUT_CMU_MISC_BUS>,
<&cmu_top CLK_DOUT_CMU_MISC_SSS>;
clock-names = "bus", "sss";
+ samsung,sysreg = <&sysreg_misc>;
};
sysreg_misc: syscon@10030000 {
@@ -662,6 +663,7 @@ cmu_peric0: clock-controller@10800000 {
<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC0_IP>;
clock-names = "oscclk", "bus", "ip";
+ samsung,sysreg = <&sysreg_peric0>;
};
sysreg_peric0: syscon@10820000 {
@@ -1208,6 +1210,7 @@ cmu_peric1: clock-controller@10c00000 {
<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
<&cmu_top CLK_DOUT_CMU_PERIC1_IP>;
clock-names = "oscclk", "bus", "ip";
+ samsung,sysreg = <&sysreg_peric1>;
};
sysreg_peric1: syscon@10c20000 {
@@ -1566,6 +1569,7 @@ cmu_hsi0: clock-controller@11000000 {
<&cmu_top CLK_DOUT_CMU_HSI0_USBDPDBG>;
clock-names = "oscclk", "bus", "dpgtc", "usb31drd",
"usbdpdbg";
+ samsung,sysreg = <&sysreg_hsi0>;
};
sysreg_hsi0: syscon@11020000 {
@@ -1637,6 +1641,7 @@ cmu_hsi2: clock-controller@14400000 {
<&cmu_top CLK_DOUT_CMU_HSI2_UFS_EMBD>,
<&cmu_top CLK_DOUT_CMU_HSI2_MMC_CARD>;
clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
+ samsung,sysreg = <&sysreg_hsi2>;
};
sysreg_hsi2: syscon@14420000 {
@@ -1697,6 +1702,7 @@ cmu_apm: clock-controller@17400000 {
clocks = <&ext_24_5m>;
clock-names = "oscclk";
+ samsung,sysreg = <&sysreg_apm>;
};
sysreg_apm: syscon@17420000 {
--
2.51.1.851.g4ebd6896fd-goog
next prev parent reply other threads:[~2025-10-29 21:30 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-29 21:29 [PATCH v2 0/4] Implement hardware automatic clock gating (HWACG) for gs101 Peter Griffin
2025-10-29 21:29 ` [PATCH v2 1/4] dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required Peter Griffin
2025-10-29 21:29 ` Peter Griffin [this message]
2025-10-29 21:29 ` [PATCH v2 3/4] clk: samsung: Implement automatic clock gating mode for CMUs Peter Griffin
2025-10-31 17:02 ` kernel test robot
2025-10-29 21:29 ` [PATCH v2 4/4] clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU Peter Griffin
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