Re: [PATCH v4 7/9] PCI: dw-rockchip: Add pme_turn_off support

Frank Li
2025-10-29T18:36:45Z

On Wed, Oct 29, 2025 at 06:56:46PM +0100, Sebastian Reichel wrote:
> Prepare Rockchip PCIe controller for system suspend support by
> adding the PME turn off operation.
>
> Co-developed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
> ---
> drivers/pci/controller/dwc/pcie-dw-rockchip.c | 44 +++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index ad4a907c991f..d887513a63d6 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -42,6 +42,7 @@
> #define PCIE_CLIENT_LD_RQ_RST_GRT FIELD_PREP_WM16(BIT(3), 1)
> #define PCIE_CLIENT_ENABLE_LTSSM FIELD_PREP_WM16(BIT(2), 1)
> #define PCIE_CLIENT_DISABLE_LTSSM FIELD_PREP_WM16(BIT(2), 0)
> +#define PCIE_CLIENT_INTR_STATUS_MSG_RX 0x04
>
> /* Interrupt Status Register Related to Legacy Interrupt */
> #define PCIE_CLIENT_INTR_STATUS_LEGACY 0x8
> @@ -61,6 +62,11 @@
>
> /* Interrupt Mask Register Related to Miscellaneous Operation */
> #define PCIE_CLIENT_INTR_MASK_MISC 0x24
> +#define PCIE_CLIENT_POWER 0x2c
> +#define PCIE_CLIENT_MSG_GEN 0x34
> +#define PME_READY_ENTER_L23 BIT(3)
> +#define PME_TURN_OFF FIELD_PREP_WM16(BIT(4), 1)
> +#define PME_TO_ACK FIELD_PREP_WM16(BIT(9), 1)
>
> /* Hot Reset Control Register */
> #define PCIE_CLIENT_HOT_RESET_CTRL 0x180
> @@ -277,8 +283,46 @@ static int rockchip_pcie_host_init(struct dw_pcie_rp *pp)
> return 0;
> }
>
> +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
> + struct device *dev = rockchip->pci.dev;
> + u32 status;
> + int ret;
> +
> + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */
> + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN);
> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN,
> + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10,
> + PCIE_PME_TO_L2_TIMEOUT_US);
> + if (ret) {
> + dev_warn(dev, "Failed to send PME_Turn_Off\n");
> + return;
> + }
> +
> + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */
> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STATUS_MSG_RX,
> + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10,
> + PCIE_PME_TO_L2_TIMEOUT_US);
> + if (ret) {
> + dev_warn(dev, "Failed to receive PME_TO_Ack\n");
> + return;
> + }
> +
> + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */
> + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATUS_MSG_RX);
> + ret = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER,
> + status, status & PME_READY_ENTER_L23,
> + PCIE_PME_TO_L2_TIMEOUT_US / 10,
> + PCIE_PME_TO_L2_TIMEOUT_US);
> + if (ret)
> + dev_err(dev, "Failed to get ready to enter L23 message\n");
> +}
> +
> static const struct dw_pcie_host_ops rockchip_pcie_host_ops = {
> .init = rockchip_pcie_host_init,
> + .pme_turn_off = rockchip_pcie_pme_turn_off,

Does common dw_pcie_pme_turn_off() work at your platform? which use iATU to
generate PME message?

I know some old chip don't support it, but I think rockchip's PCIe should
new enough.

Frank

> };
>
> /*
>
> --
> 2.51.0
>