From: Chuan Liu via B4 Relay <devnull+chuan.liu.amlogic.com@kernel.org>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Jerome Brunet <jbrunet@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Chuan Liu <chuan.liu@amlogic.com>,
da@libre.computer
Subject: [PATCH v2 5/5] clk: amlogic: Change the active level of l_detect
Date: Thu, 30 Oct 2025 13:24:15 +0800 [thread overview]
Message-ID: <20251030-optimize_pll_driver-v2-5-37273f5b25ab@amlogic.com> (raw)
In-Reply-To: <20251030-optimize_pll_driver-v2-0-37273f5b25ab@amlogic.com>
From: Chuan Liu <chuan.liu@amlogic.com>
l_detect controls the enable/disable of the PLL lock-detect module.
The enable signal is normally active-high. This design ensures that
the module remains disabled during the power-on process, preventing
power fluctuations from affecting its operating state.
For A1, the l_detect signal is active-low:
0 -> Enable lock-detect module;
1 -> Disable lock-detect module.
Here, a flag CLK_MESON_PLL_L_DETECT_N is added to handle cases like
A1, where the signal is active-low.
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
---
drivers/clk/meson/a1-pll.c | 1 +
drivers/clk/meson/clk-pll.c | 16 ++++++++++++----
drivers/clk/meson/clk-pll.h | 2 ++
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c
index 1f82e9c7c14e..bfe559c71402 100644
--- a/drivers/clk/meson/a1-pll.c
+++ b/drivers/clk/meson/a1-pll.c
@@ -137,6 +137,7 @@ static struct clk_regmap a1_hifi_pll = {
.range = &a1_hifi_pll_range,
.init_regs = a1_hifi_pll_init_regs,
.init_count = ARRAY_SIZE(a1_hifi_pll_init_regs),
+ .flags = CLK_MESON_PLL_L_DETECT_N
},
.hw.init = &(struct clk_init_data){
.name = "hifi_pll",
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index c6eebde1f516..d729e933aa1c 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -384,8 +384,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
meson_parm_write(clk->map, &pll->rst, 1);
/* Disable the PLL lock-detect module */
- if (MESON_PARM_APPLICABLE(&pll->l_detect))
- meson_parm_write(clk->map, &pll->l_detect, 1);
+ if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
+ if (pll->flags & CLK_MESON_PLL_L_DETECT_N)
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+ else
+ meson_parm_write(clk->map, &pll->l_detect, 0);
+ }
/* Enable the pll */
meson_parm_write(clk->map, &pll->en, 1);
@@ -413,8 +417,12 @@ static int meson_clk_pll_enable(struct clk_hw *hw)
udelay(20);
/* Enable the lock-detect module */
- if (MESON_PARM_APPLICABLE(&pll->l_detect))
- meson_parm_write(clk->map, &pll->l_detect, 0);
+ if (MESON_PARM_APPLICABLE(&pll->l_detect)) {
+ if (pll->flags & CLK_MESON_PLL_L_DETECT_N)
+ meson_parm_write(clk->map, &pll->l_detect, 0);
+ else
+ meson_parm_write(clk->map, &pll->l_detect, 1);
+ }
if (meson_clk_pll_wait_lock(hw)) {
/* disable PLL when PLL lock failed. */
diff --git a/drivers/clk/meson/clk-pll.h b/drivers/clk/meson/clk-pll.h
index 949157fb7bf5..83295a24721f 100644
--- a/drivers/clk/meson/clk-pll.h
+++ b/drivers/clk/meson/clk-pll.h
@@ -29,6 +29,8 @@ struct pll_mult_range {
#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
#define CLK_MESON_PLL_NOINIT_ENABLED BIT(1)
+/* l_detect signal is active-low */
+#define CLK_MESON_PLL_L_DETECT_N BIT(2)
struct meson_clk_pll_data {
struct parm en;
--
2.42.0
next prev parent reply other threads:[~2025-10-30 5:24 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-30 5:24 [PATCH v2 0/5] clk: amlogic: optimize the PLL driver Chuan Liu via B4 Relay
2025-10-30 5:24 ` [PATCH v2 1/5] clk: amlogic: Fix out-of-range PLL frequency setting Chuan Liu via B4 Relay
2025-10-30 5:24 ` [PATCH v2 2/5] clk: amlogic: Improve the issue of PLL lock failures Chuan Liu via B4 Relay
2025-10-30 8:41 ` Jerome Brunet
2025-10-30 9:09 ` Chuan Liu
2025-10-30 5:24 ` [PATCH v2 3/5] clk: amlogic: Add handling for PLL lock failure Chuan Liu via B4 Relay
2025-10-30 8:32 ` Jerome Brunet
2025-10-30 9:15 ` Chuan Liu
2025-10-30 11:48 ` Chuan Liu
2025-10-30 5:24 ` [PATCH v2 4/5] clk: amlogic: Optimize PLL enable timing Chuan Liu via B4 Relay
2025-10-30 8:38 ` Jerome Brunet
2025-10-30 9:23 ` Chuan Liu
2025-10-30 5:24 ` Chuan Liu via B4 Relay [this message]
2025-10-30 8:40 ` [PATCH v2 5/5] clk: amlogic: Change the active level of l_detect Jerome Brunet
2025-10-30 9:27 ` Chuan Liu
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