From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9DF30CCFA00 for ; Thu, 30 Oct 2025 13:48:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:CC:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Y5xYksDJSoM3FsK+l+zIqMequ4QeSt0WoTpN/qOQ7Jk=; b=KwTJ9RVbEMbCnwZy1l0jPJoV6O +/1JVe5bubruXq3ThmL6WIlb6Arz32wlUr4yE0A8sDaYh8s7KBUfpLIfCcj9ZL2gdWh+04PEMGuGf UeXco6/cXiOU09SK3dCc5QheiIKVdkPEAzhy0sqTEl/cyKw7RbcEakPfx+N8/0AE1biy8TmEZiA6U bhB+LbKeykJYH4McO6yovlEiBg5YKycJwTCTKYnA6fYKo5/mFa+zFzpxAPSQ93zra1RlIRA986EKZ WRVTfjYQV0M3/IWOS4GxNeMmHwWEutqEDA//p+horgaMK5Pbirns0yFpoTt9jjKBFUzM0yE7WF6Ql U+fyIgcw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vET0R-00000004E5z-3bz3; Thu, 30 Oct 2025 13:47:59 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vET06-00000004DsU-3tao; Thu, 30 Oct 2025 13:47:40 +0000 X-UUID: fd7e25e8b59611f09f706fa2197c6ceb-20251030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Y5xYksDJSoM3FsK+l+zIqMequ4QeSt0WoTpN/qOQ7Jk=; b=c7jbqvkVOxKoOGArFramxkDhB0ox3st+ZBEt4+qahh+1pA9rGY4M6PRZUEvRKY6v14ENsAs0oeiH8o1rO1kHDM4zaeVz+huOdWkKGoXALJTigj7q5knk0B/WVifzbkOwh/+YUg4obkCwIUuMx4qWhWOcv/88Gib20+AmhC5EaY0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.6,REQID:b0231c0b-d046-4b8f-8757-619154a71eec,IP:0,UR L:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-25 X-CID-META: VersionHash:a9d874c,CLOUDID:7ac8db6a-d4bd-4ab9-8221-0049857cc502,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|888|898,TC:-5,Content: 0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:nil,COL:0,OS I:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: fd7e25e8b59611f09f706fa2197c6ceb-20251030 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 299782356; Thu, 30 Oct 2025 06:47:35 -0700 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.26; Thu, 30 Oct 2025 21:47:31 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1748.26 via Frontend Transport; Thu, 30 Oct 2025 21:47:31 +0800 From: Jack Hsu To: , , , , , , , , , , , , , , , , , , , , , , CC: , , , , , , , , , , Jack Hsu Subject: [PATCH v6 10/11] arm64: dts: mediatek: add properties for MT6359 Date: Thu, 30 Oct 2025 21:44:42 +0800 Message-ID: <20251030134541.784011-11-jh.hsu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20251030134541.784011-1-jh.hsu@mediatek.com> References: <20251030134541.784011-1-jh.hsu@mediatek.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251030_064739_013126_7CE86DED X-CRM114-Status: GOOD ( 13.56 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add properties of rtc fg (Fuel Gauge), external crystal and auxadc definition for mt6359 pmic. Signed-off-by: Jack Hsu --- arch/arm64/boot/dts/mediatek/mt6359.dtsi | 20 ++++++++++ include/dt-bindings/iio/mt635x-auxadc.h | 50 ++++++++++++++++++++++++ 2 files changed, 70 insertions(+) create mode 100644 include/dt-bindings/iio/mt635x-auxadc.h diff --git a/arch/arm64/boot/dts/mediatek/mt6359.dtsi b/arch/arm64/boot/dts/mediatek/mt6359.dtsi index 467d8a4c2aa7..cc7053bdd292 100644 --- a/arch/arm64/boot/dts/mediatek/mt6359.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt6359.dtsi @@ -3,6 +3,8 @@ * Copyright (C) 2022 MediaTek Inc. */ +#include + &pwrap { pmic: pmic { compatible = "mediatek,mt6359"; @@ -302,6 +304,24 @@ mt6359_vsram_others_sshub_ldo: ldo_vsram_others_sshub { mt6359rtc: rtc { compatible = "mediatek,mt6358-rtc"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + fginit: fginit { + reg = <0 0x1>; + bits = <0 8>; + }; + + fgsoc: fgsoc { + reg = <1 0x1>; + bits = <0 8>; + }; + + ext32k: ext32k { + reg = <2 0x1>; + bits = <6 1>; + }; }; }; }; diff --git a/include/dt-bindings/iio/mt635x-auxadc.h b/include/dt-bindings/iio/mt635x-auxadc.h new file mode 100644 index 000000000000..69ba13a7b9ec --- /dev/null +++ b/include/dt-bindings/iio/mt635x-auxadc.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2020 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_MT635X_AUXADC_H +#define _DT_BINDINGS_MT635X_AUXADC_H + +/* PMIC MT635x AUXADC channels */ +#define AUXADC_BATADC 0x00 +#define AUXADC_ISENSE 0x01 +#define AUXADC_VCDT 0x02 +#define AUXADC_BAT_TEMP 0x03 +#define AUXADC_BATID 0x04 +#define AUXADC_CHIP_TEMP 0x05 +#define AUXADC_VCORE_TEMP 0x06 +#define AUXADC_VPROC_TEMP 0x07 +#define AUXADC_VGPU_TEMP 0x08 +#define AUXADC_ACCDET 0x09 +#define AUXADC_VDCXO 0x0a +#define AUXADC_TSX_TEMP 0x0b +#define AUXADC_HPOFS_CAL 0x0c +#define AUXADC_DCXO_TEMP 0x0d +#define AUXADC_VBIF 0x0e +#define AUXADC_IMP 0x0f +#define AUXADC_IMIX_R 0x10 +#define AUXADC_VTREF 0x11 +#define AUXADC_VSYSSNS 0x12 +#define AUXADC_VIN1 0x13 +#define AUXADC_VIN2 0x14 +#define AUXADC_VIN3 0x15 +#define AUXADC_VIN4 0x16 +#define AUXADC_VIN5 0x17 +#define AUXADC_VIN6 0x18 +#define AUXADC_VIN7 0x19 + +#define AUXADC_CHAN_MIN AUXADC_BATADC +#define AUXADC_CHAN_MAX AUXADC_VIN7 + +#define ADC_PURES_100K (0) +#define ADC_PURES_30K (1) +#define ADC_PURES_400K (2) +#define ADC_PURES_OPEN (3) + +#define ADC_PURES_100K_MASK (ADC_PURES_100K << 8) +#define ADC_PURES_30K_MASK (ADC_PURES_30K << 8) +#define ADC_PURES_400K_MASK (ADC_PURES_400K << 8) +#define ADC_PURES_OPEN_MASK (ADC_PURES_OPEN << 8) + +#endif /* _DT_BINDINGS_MT635X_AUXADC_H */ -- 2.45.2