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Thu, 30 Oct 2025 23:30:05 -0700 From: Ashish Mhetre To: , , , , , , , , , CC: , , , , , , Ashish Mhetre Subject: [PATCH 2/3] dt-bindings: iommu: Add NVIDIA Tegra CMDQV support Date: Fri, 31 Oct 2025 06:29:58 +0000 Message-ID: <20251031062959.1521704-3-amhetre@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20251031062959.1521704-1-amhetre@nvidia.com> References: <20251031062959.1521704-1-amhetre@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF00004FBF:EE_|DM6PR12MB4059:EE_ X-MS-Office365-Filtering-Correlation-Id: b612642d-25ec-4447-fb4b-08de1846f96a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700013|1800799024|13003099007|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?BpIayLrNrgqJ3w2hBnpZDBXdV2/YPjsjIR1VG2ITlE68BpOM+yXGn+L0C982?= =?us-ascii?Q?FTRMPEltioZrcnnEsy6CDJhbR6z/vZJDR7jNTSbZb+WnD2AqTneTrfD1Nnvl?= =?us-ascii?Q?mGLAKPs8hnoQGG93Zn36+f8ysw1o6inYks2oMqt0+VLEfxjgUFGSqwFu8CeH?= =?us-ascii?Q?Y/O2kFFSbpiINyv/z2wa4FR/KAaPUrEieq/J3umRTVakQtQW0KiD4P0r5xcj?= =?us-ascii?Q?QpWJdbjrYHqlP5BrZ78ViRNzdW4PPcZsp5Sb99DWn+fMbq0viWlgAiTLZU/+?= =?us-ascii?Q?5UMpNweJoJP6UBigGFEqVS053RVgpRO7V7wUGhjeloo6f18l+Xywugm9pD0k?= =?us-ascii?Q?4H3JN+RdnSP7ATZzY1Tgms1zK6yspgVCGGVUvGFMvK9XPOSoxlUUxykkCQDZ?= =?us-ascii?Q?qtZH9jIK98ElVJhqocHPytZ6dzzpdDHg8Yj/dUIZEnj0soYYVvl+FXlehDOW?= =?us-ascii?Q?DkPD/0pd0Ie1thpniJyLFVpUy7fo1Qf1cE/AiGkRbi9kxJORPmHFDCk+tHYM?= =?us-ascii?Q?mhe4o+CbfDWnXcjSYSriMC21Y5r5XgQvEEW4zpcnJefWgKWURUh2axBA9qgy?= =?us-ascii?Q?iAKwMZpexcgKO7SEaSHURc/zOMSQRfbENBImfMcR/Zl+MuGfXDLUUfkLED5i?= =?us-ascii?Q?WVh4jyrTSwPbqKOgShXnFEbYm6BDVnowBFEb3jXIZsC1AmSmT6bOMDb4b2RE?= =?us-ascii?Q?0hk8o2GzkplMpo5V25JuBmNv8Wl6lEiZGyzRWtxlr41WeMVzg2mbxWASYIUo?= =?us-ascii?Q?wJYuevU4AM/CZcqcxexedez95B8bkAccYS++AdF/FrfoNhixrct3dsvnBQ4b?= =?us-ascii?Q?U2rSVcHpwxCZ0Iyf6BB/O1fwNl86rWtNZtf8yVVh0xX7UA0TvlfM8RpWZjre?= =?us-ascii?Q?azGhNsyTIjoSeSNEQF/6t+OBO3xAPkGo/XVBhC041XW0z4qbH+QSZjHRAnBY?= =?us-ascii?Q?MGjksCp+O7yA+uU7PJSzCIe3bPH0vKr9kCzrjqKt4yyE+m4dVVyyRvmbQh8C?= =?us-ascii?Q?/d8BmGjXxzb9QjyUQg5Va3/LcXDdIB34RUitdePoc0JV4XPr7xVlUsL3jVRt?= =?us-ascii?Q?iY1ed8JoOlixQbVBdQv42eExg7pfnAAlOxONCW/s/70poOFi54lIwCYkcWMr?= =?us-ascii?Q?D/CvJAgcw7YEV3/MOVehm72zbNu+ryUvIyjEPlhLnR2ZtkXaqiC4DP5BbV1F?= =?us-ascii?Q?lRqnbMLH68RlHsGM0JMp2OzWm7fldiwtvEXfFvMvN+r/kWM7iICJCjNTIxwL?= =?us-ascii?Q?Txqv3Ei0RS7b7YveAcdCWPDIjD8pchfCaXSS1Aadht8wGBFdRf+tAuKDn42q?= =?us-ascii?Q?V512rHE6AHeddcunW8V5YU+F0gpe4YjNGQE52a3NH05JzPwi+8PQBeD2u0sN?= =?us-ascii?Q?wYrnj4fIH0RYe5DLIJlKo6y64vgx3vUogBFyb5n+RykdpHCGgbA9K26zE/ob?= =?us-ascii?Q?Kl+v/yNWtVDyP9pDHkOGgQBqF95bgMTeM66UJ94aZyzzQr2s48zhW5s7AfLE?= =?us-ascii?Q?NKeg3TcR70UIrs/5bL3wFWy9qas4nlpVY7IsTqR8eryMvebgIn2Enl3oOByP?= =?us-ascii?Q?eAI/VeAbRle6kSjWNZ+QdYY/vnyFELk9+/9uplPy?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(7416014)(82310400026)(36860700013)(1800799024)(13003099007)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 06:30:24.2691 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b612642d-25ec-4447-fb4b-08de1846f96a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF00004FBF.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4059 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251030_233031_108166_05AE3EDE X-CRM114-Status: GOOD ( 15.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The Command Queue Virtualization (CMDQV) hardware is part of the SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in virtualizing the command queue for the SMMU. Add a new device tree binding document for nvidia,tegra264-cmdqv. Also update the arm,smmu-v3 binding to include an optional nvidia,cmdqv property. This property is a phandle to the CMDQV device node, allowing the SMMU driver to associate with its corresponding CMDQV instance. Signed-off-by: Ashish Mhetre --- .../bindings/iommu/arm,smmu-v3.yaml | 10 ++++ .../bindings/iommu/nvidia,tegra264-cmdqv.yaml | 46 +++++++++++++++++++ 2 files changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml index 75fcf4cb52d9..edc0c20a0c80 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml @@ -58,6 +58,15 @@ properties: msi-parent: true + nvidia,cmdqv: + description: | + A phandle to its pairing CMDQV extension for an implementation on NVIDIA + Tegra SoC. + + If this property is absent, CMDQ-Virtualization won't be used and SMMU + will only use its own CMDQ. + $ref: /schemas/types.yaml#/definitions/phandle + hisilicon,broken-prefetch-cmd: type: boolean description: Avoid sending CMD_PREFETCH_* commands to the SMMU. @@ -92,4 +101,5 @@ examples: dma-coherent; #iommu-cells = <1>; msi-parent = <&its 0xff0000>; + nvidia,cmdqv = <&cmdqv>; }; diff --git a/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml new file mode 100644 index 000000000000..f22c370278a3 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/nvidia,tegra264-cmdqv.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 CMDQV +description: | + The CMDQ-Virtualization hardware block is part of the SMMUv3 implementation + on Tegra264 SoCs. It assists in virtualizing the command queue for the SMMU. + +maintainers: + - NVIDIA Corporation + +properties: + compatible: + const: nvidia,tegra264-cmdqv + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: cmdqv + +required: + - compatible + - reg + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + #include + + cmdqv: cmdqv@8105200000 { + compatible = "nvidia,tegra264-cmdqv"; + reg = <0x81 0x05200000 0x0 0x00830000>; + interrupts = ; + interrupt-names = "cmdqv"; + }; -- 2.25.1