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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8743741604E2; Fri, 31 Oct 2025 15:30:03 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, broonie@kernel.org Cc: linux-spi@vger.kernel.org, michal.simek@amd.com, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, "jun.guo" Subject: [PATCH v3 0/3] spi-cadence: support transmission with bits_per_word of 16 and 32 Date: Fri, 31 Oct 2025 15:30:00 +0800 Message-Id: <20251031073003.3289573-1-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB8A:EE_|SE1PPF5FAD0D4F8:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 13e51e3e-6301-4735-ecfb-08de184f4fce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?emshA/ZEz6br03Kiat2ve5dmmi/eowhV3HYsD6SqRO4MpHMuRM++zHwCiYYf?= =?us-ascii?Q?sC32ahg3xSxKhWKpHyv2LhGN/Ekz57k6LFszrfY9fWt/zWDpnJJaM3LM9bzx?= =?us-ascii?Q?eWeMQqvkXnjx5VuZSPRg+aUIQjLyUjAFXAT5L/jZ62b80qOJSLmTYavUgMh/?= =?us-ascii?Q?vqsoyTYpcBnc9bpA2HiMfYQvHG+5Qwhn+xytolmOBg6fsTohYA66bQqtzEjF?= =?us-ascii?Q?cSMMWHBZIUC4MPFQLhgIRVQJDzGCJSCmB9uY+BhKMbpaviQf3HlZgpuJEp7d?= =?us-ascii?Q?NWnTHfl2s8mWrLr6GKg77mQH0GksKtOT57ABgDYbCG9x5NDdU81nQDbCskZ0?= =?us-ascii?Q?lamtT3OCAN5OYOigwePjFe+isXnaN7hIMcGJZiDrHxRwf6Noh5R2VWgbDF47?= =?us-ascii?Q?k4QuDSP/cocCKMqfO3fCBMsrlxFpg35VdRc4pED95koQP93qaUmi+kqFBR2n?= =?us-ascii?Q?0X2muVLiALcanvUf1tF+uYFXBDs+xqJ4kxv+8cKMqN/oOd2uB49F6MGOjiBe?= =?us-ascii?Q?nBtr5gFGDiF/raeSrUMWNu1ZzCRT+smZV3vktBWGAbs2AdYFrO82EeTA28m8?= =?us-ascii?Q?THAJRdx+/ch9LAfmPYwza/8MbqbQ4dfTQC0Yg9u2mJliSmcphtXfiV209syN?= =?us-ascii?Q?2UjhfjKbTWFnA6wpG5o1NXyywdahOdMYZhEbmgaEa92AE9zhEyV7nGcTxLZ0?= =?us-ascii?Q?zhzkKoHn7FwXmRVU96lCQPvucICARH2FP255filnJZfFmzDVbIoYfnXUJ1GK?= =?us-ascii?Q?YNkh77lfaJ/sYRu26HPrH551PfJ/bvdCxP0DYFIHaIlsy5lQt6ZGfE4T16Y/?= =?us-ascii?Q?Yujcx/rZLn2q83ro8TnC8unq+O5zjrPrIbjvVpcI9Pmzi3SJotgu2XRPdqdc?= =?us-ascii?Q?H4LflPLQkb1+NZRDHydQhsXWFLzxhaR0ptqp7K5IWs0rTIbH0W6DNE9zvtQL?= =?us-ascii?Q?kq41c+9VnUjqWzZLsTU7mIFZMIwzpyZTHP5me7gceP5zNqXRanlhu3juNstW?= =?us-ascii?Q?8ynC0XQUV3SwYOLKgwgJXvHvJt95dJDD3yqPypBMSU+LTme2w7H0DwS3NGY/?= =?us-ascii?Q?dzwpUQCnBPwShssgDrNYIxcRbLgajLy9J0m11D2d41KEXpuLFVNATbsvvTM7?= =?us-ascii?Q?GfYPthv4uRe/6r/ahZItf1H9z5wRZA2P6AIuxlasooX+3YxygjfEWmlDS6aP?= =?us-ascii?Q?w0jZ87hEttAxjTv9z7O7Y0yK7y1yjrgpQuigl7QkM+dqx3W57tbVVVqk0MAe?= =?us-ascii?Q?3+3qSEpzL2z8uQW0aDuP/dC+mrFR7nd6ouuU/9uQ3t8fIuq+MhQuXIIaNGB7?= =?us-ascii?Q?UP248FWCnZz6wlsuQ2C8XycxGbDF1Sl6FDUknG4msa0sXYQj5bdJhuFkgYOl?= =?us-ascii?Q?koAvhPdgdcQakO6fNLq0/7iXkfqM7xxpbdX1uDNT4kzdhHxvDgV8I0GCBYVs?= =?us-ascii?Q?2bfbQFrKKEXcOI88GsjSZDowpFrOjrt3ApNUMq8GaUX0zH0zs91/6kRJi/nI?= =?us-ascii?Q?wrpUZEFR10v8uO1aXR1NUP1ZGNi7htZ/fVu3zNdFJ4k/zyuknu9x6rRCHn4M?= =?us-ascii?Q?KQfYGqPOnf8oDo44sUQ=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Oct 2025 07:30:05.0961 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13e51e3e-6301-4735-ecfb-08de184f4fce X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB8A.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE1PPF5FAD0D4F8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251031_003015_094433_0FA94135 X-CRM114-Status: GOOD ( 13.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: "jun.guo" The Cadence SPI IP supports configurable FIFO data widths during integration. On some SoCs, the FIFO data width is designed to be 16 or 32 bits at the chip design stage. However, the current driver only supports communication with an 8-bit FIFO data width. Therefore, these patches are added to enable the driver to support communication with 16-bit and 32-bit FIFO data widths. This series introduces the following enhancements for Cadence SPI controller support on arm64 platforms: Patch 1: Add a compatible string "cix,sky1-spi-r1p6" for the cix sky1 SoC. Patch 2: Update DT binding docs to support cix sky1 SoC. Patch 3: Enhance the SPI Cadence driver to support data transmission with bits_per_word values of 16 and 32. The CIX Sky1 SPI supported patch is added: https://lore.kernel.org/all/20250919013118.853078-1-jun.guo@cixtech.com/ The patches have been tested on CIX SKY1 platform. Changes for v3: - Rebase the dt-bindings modification on top of the latest patches in spi/for-next to make the patch more minimal. Changes for v2: - Remove the fifo-width property and add a compatible string for the cix sky1 SoC to control the FIFO data width configuration. Jun Guo (3): dt-bindings: spi: spi-cadence: update DT binding docs to support cix sky1 SoC spi: spi-cadence: supports transmission with bits_per_word of 16 and 32 arm64: dts: cix: add a compatible string for the cix sky1 SoC .../devicetree/bindings/spi/spi-cadence.yaml | 1 + arch/arm64/boot/dts/cix/sky1.dtsi | 4 +- drivers/spi/spi-cadence.c | 106 +++++++++++++++--- 3 files changed, 96 insertions(+), 15 deletions(-) -- 2.34.1