From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E2F95CCF9FA for ; Fri, 31 Oct 2025 11:17:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=VG2ZXFA5ya8adW1y1VrqLqVg7XoS2peqnveGWzUthrY=; b=0jODlZpCpSgYL9taKsz+5UIMEh 8Wql4wt32y3qVC/QjZWRr4c9nleFF6FcC1j77ojQEFSjbYb8lO2PQcJITy6sGEN1euXsjw4zQR536 r4UTLUqOsJFU3rCd33uAJIN/PLLR76yzQf0lMyrA4z1BCds5xFHIayPX3iSFvnVn1tG7TnUQMiRgh JRGfNcrkuSD4KRi236chEJlzmSt7671PMm/Zmi7SpjSSMCT9KAhnt3+UE5jQavm5Dk7CyOqOeouE4 /WSjBchx0ZJcXQwJbK+bEHnTbHHBNfUIaEiXSkT3xqFZ/fp89MrzzIACOutLTPPYPKQiOV6telLdB FZ+5BkTQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vEn8F-0000000605V-2LHc; Fri, 31 Oct 2025 11:17:23 +0000 Received: from frasgout.his.huawei.com ([185.176.79.56]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vEn8B-0000000603z-1oGh for linux-arm-kernel@lists.infradead.org; Fri, 31 Oct 2025 11:17:21 +0000 Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTPS id 4cydjQ6cF3zJ46bm; Fri, 31 Oct 2025 19:16:58 +0800 (CST) Received: from dubpeml100005.china.huawei.com (unknown [7.214.146.113]) by mail.maildlp.com (Postfix) with ESMTPS id D0B20140370; Fri, 31 Oct 2025 19:17:11 +0800 (CST) Received: from SecurePC-101-06.huawei.com (10.122.19.247) by dubpeml100005.china.huawei.com (7.214.146.113) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 31 Oct 2025 11:17:10 +0000 From: Jonathan Cameron To: Conor Dooley , Catalin Marinas , , , , , Dan Williams , "H . Peter Anvin" , Peter Zijlstra , Andrew Morton , Arnd Bergmann , Drew Fustini , Linus Walleij , Alexandre Belloni , Krzysztof Kozlowski CC: , Will Deacon , Davidlohr Bueso , , Yushan Wang , Lorenzo Pieralisi , Mark Rutland , Dave Hansen , Thomas Gleixner , Ingo Molnar , Borislav Petkov , , Andy Lutomirski , Dave Jiang Subject: [PATCH v5 0/6] Cache coherency management subsystem Date: Fri, 31 Oct 2025 11:17:03 +0000 Message-ID: <20251031111709.1783347-1-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.48.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.122.19.247] X-ClientProxiedBy: lhrpeml500010.china.huawei.com (7.191.174.240) To dubpeml100005.china.huawei.com (7.214.146.113) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251031_041719_758035_06E12058 X-CRM114-Status: GOOD ( 28.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Support system level interfaces for cache maintenance as found on some ARM64 systems. It is expected that systems using other CPU architectures (such as RiscV) that support CXL memory and allow for native OS flows will also use this. This is needed for correct functionality during various forms of memory hotplug (e.g. CXL). Typical hardware has MMIO interface found via ACPI DSDT. A system will often contain multiple hardware instances. Includes parameter changes to cpu_cache_invalidate_memregion() but no functional changes for architectures that already support this call. How to merge? - Current suggestion would be via Conor's drivers/cache tree which routes through the SoC tree. * Andrew Morton has expressed he is fine with the MM related changes going via another appropriate tree. * CXL maintainers expressed that they don't consider it appropriate to go through theit tree. * The tiny touching of Arm specific code has an ack from Catalin. v5: Changes called out in individual patches. Comment and patch description updates to make the following clearer. - Difference from cache-coherence operations for non-coherent DMA. Longer term it may make sense to share infrastructure but for now we have two parallel systems as there would be near zero overlap in code or functionality. - Why multiple agent handling is necessary and what that means for the HiSilicon HHAs in our systems + the driver inclued in this set. v4: (Small changes called out in each patch) - Drop the ACPI driver. It has done it's job as a second implementation to help with generality testing. I have heard zero interest in actually doing the specification work needed to make that official. Easy to bring back if needed in future. I have it locally still as a second test case. - Add a cpu_cache_invalidate_all() helper for the 0,-1 case that is used to indicate everything should be flushed as no fine grained range info available. - Simplify the necessary symbols to be selected by architectures by making CONFIG_GENERIC_CPU_CACHE_MAINTENANCE select ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION - Avoid naming mentioning devices as there is no struct device. - Use a kref so as to have something on which a _put() operation makes sense avoiding rather confusing freeing of an internal structure pointer that was seen in v3. - Gather tags given. - Various minor things like typos, header tweaks etc. Thanks to all who reviewed v3. On current ARM64 systems (and likely other architectures) the implementation of cache flushing need for actions such as CXL memory hotplug e.g. cpu_cache_invalidate_memregion(), is performed by system components outside of the CPU, controlled via either firmware or MMIO interfaces. These control units run the necessary coherency protocol operations to cause the write backs and cache flushes to occur asynchronously. They allow filtering by PA range to reduce disruption to the system. Systems supporting this interface must be designed to ensure that, when complete, all cache lines in the range are in invalid state or clean state (prefetches may have raced with the invalidation). This must include memory-side caches and other non architectural caches beyond the Point of Coherence (ARM terminology) such that writes will reach memory even after OS programmable address decoders are modified (for CXL this is any HDM decoders that aren't locked). Software will guarantee that no writes to these memory ranges race with this operation. Whilst this is subtly different from write backs must reach the physical memory that difference probably doesn't matter to those reading this series. The often distributed nature of the relevant coherency management units (e.g. due to interleaving) requires the appropriate commands to be issued to multiple (potentially heterogeneous) units. To enable this a registration framework is provided to which drivers may register a set of callbacks. Upon a request for a cache maintenance operation the framework iterates over all registered callback sets, calling first a command to write back and invalidate, and then optionally a command to wait for completion. Filtering on relevance if a give request is left to the individual drivers. In this version only one driver is included. This is the HiSilicon Hydra Home Agent driver which controls hardware found on some of our relevant server SoCs. Also available (I can post if anyone is interested) is an ACPI driver based on a firmware interface that was in a public PSCI specification alpha version QEMU emulation code at http://gitlab.com/jic23/qemu cxl-2025-03-20 Notes: - I don't particularly like defining 'generic' infrastructure with so few implementations. If anyone can point me at docs for another one or two, or confirm that they think this is fine that would be great! The converse to this is I don't want to wait longer for those to surface given the necessity to support this one platform that I do know about! Jonathan Cameron (3): memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() arm64: Select GENERIC_CPU_CACHE_MAINTENANCE MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header Yicong Yang (2): memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Yushan Wang (1): cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent MAINTAINERS | 3 + arch/arm64/Kconfig | 1 + arch/x86/mm/pat/set_memory.c | 2 +- drivers/cache/Kconfig | 15 +++ drivers/cache/Makefile | 2 + drivers/cache/hisi_soc_hha.c | 194 ++++++++++++++++++++++++++++++++ drivers/cxl/core/region.c | 5 +- drivers/nvdimm/region.c | 2 +- drivers/nvdimm/region_devs.c | 2 +- include/linux/cache_coherency.h | 61 ++++++++++ include/linux/memregion.h | 16 ++- lib/Kconfig | 4 + lib/Makefile | 2 + lib/cache_maint.c | 138 +++++++++++++++++++++++ 14 files changed, 439 insertions(+), 8 deletions(-) create mode 100644 drivers/cache/hisi_soc_hha.c create mode 100644 include/linux/cache_coherency.h create mode 100644 lib/cache_maint.c -- 2.48.1