[PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Siddharth Vadapalli]

The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
correction has been implemented/enforced by the updates to:
a) Device-Tree binding for CPSW [0]
b) Driver for CPSW [1]
c) Driver for CPSW MAC Port's GMII [2]

To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
'rgmii-id'.

[0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
[1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
[2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

Hello,

This patch is based on linux-next tagged next-20251024.

Regards,
Siddharth.

 arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi          | 2 +-
 arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi           | 2 +-
 arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi           | 2 +-
 arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi               | 2 +-
 arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts           | 2 +-
 arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi           | 3 +--
 arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi         | 2 +-
 arch/arm64/boot/dts/ti/k3-am62a7-sk.dts                  | 2 +-
 arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi          | 2 +-
 arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi          | 2 +-
 arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi              | 2 +-
 arch/arm64/boot/dts/ti/k3-am62p5-sk.dts                  | 4 ++--
 arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi       | 2 +-
 arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi           | 2 +-
 arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi          | 2 +-
 arch/arm64/boot/dts/ti/k3-am642-evm.dts                  | 4 ++--
 arch/arm64/boot/dts/ti/k3-am642-sk.dts                   | 4 ++--
 arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts   | 2 +-
 arch/arm64/boot/dts/ti/k3-am654-base-board.dts           | 2 +-
 arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts           | 2 +-
 arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts         | 2 +-
 arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi          | 2 +-
 arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts         | 2 +-
 arch/arm64/boot/dts/ti/k3-am69-sk.dts                    | 2 +-
 arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts    | 2 +-
 arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts       | 2 +-
 arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts    | 2 +-
 arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso  | 8 ++++----
 arch/arm64/boot/dts/ti/k3-j721e-sk.dts                   | 2 +-
 arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts   | 2 +-
 arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 2 +-
 arch/arm64/boot/dts/ti/k3-j722s-evm.dts                  | 2 +-
 arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi  | 4 ++--
 33 files changed, 40 insertions(+), 41 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
index eeca643fedbe..985963774c00 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
@@ -214,7 +214,7 @@ &cpsw3g {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy1>;
 	bootph-all;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
index 5c1284b802ad..3d1406acf680 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
@@ -74,7 +74,7 @@ &cpsw_port1 {
 /* Verdin ETH_2_RGMII */
 &cpsw_port2 {
 	phy-handle = <&cpsw3g_phy1>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
index 71c29eab0eee..844f59f772e1 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
@@ -268,7 +268,7 @@ &cpsw_port1 {
 /* Verdin ETH_2_RGMII */
 &cpsw_port2 {
 	phy-handle = <&cpsw3g_phy1>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
index dc4b228a9fd7..2a7242a2fef8 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
@@ -845,7 +845,7 @@ &cpsw3g {
 /* Verdin ETH_1 (On-module PHY) */
 &cpsw_port1 {
 	phy-handle = <&cpsw3g_phy0>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "disabled";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
index 7028d9835c4a..7b9ae467e95a 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
+++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
@@ -593,7 +593,7 @@ &cpsw3g {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
index fe0b98e1d105..7eb9066bff82 100644
--- a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
@@ -215,8 +215,7 @@ &cpsw3g {
 };
 
 &cpsw_port2 {
-	/* PCB provides an internal delay of 2ns */
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy1>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
index b3d012a5a26a..b24a63feeab8 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
@@ -192,7 +192,7 @@ &cpsw3g {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy1>;
 	bootph-all;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
index af591fe6ae4f..de850307912c 100644
--- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
@@ -731,7 +731,7 @@ &phy_gmii_sel {
 
 &cpsw_port1 {
 	status = "okay";
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	bootph-all;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
index 0679d76f31bd..a0d5b15fc147 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
@@ -78,7 +78,7 @@ &cpsw_port1 {
 /* Verdin ETH_2_RGMII */
 &cpsw_port2 {
 	phy-handle = <&carrier_eth_phy>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
index 317c8818f9ee..04f13edcb166 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
@@ -275,7 +275,7 @@ &cpsw_port1 {
 /* Verdin ETH_2_RGMII */
 &cpsw_port2 {
 	phy-handle = <&carrier_eth_phy>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
index 99810047614e..5e050cbb9eaf 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
@@ -813,7 +813,7 @@ som_eth_phy: ethernet-phy@0 {
 /* Verdin ETH_1 (On-module PHY) */
 &cpsw_port1 {
 	phy-handle = <&som_eth_phy>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "disabled";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index a064a632680e..f04cf2d23d84 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -541,14 +541,14 @@ &cpsw3g {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	status = "okay";
 	bootph-all;
 };
 
 &cpsw_port2 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy1>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
index aab74d6019b0..d6e70ee15938 100644
--- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
@@ -291,7 +291,7 @@ &cpsw3g {
 };
 
 &cpsw_port2 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy3>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
index 58f78c0de292..50ed859ae06c 100644
--- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
@@ -438,7 +438,7 @@ &cpsw3g {
 
 &cpsw_port1 {
 	bootph-all;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
index 02ef1dd92eaa..d64fb81b04e2 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
@@ -178,7 +178,7 @@ cpsw3g_phy1: ethernet-phy@1 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy1>;
 	bootph-all;
 	status = "okay";
diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
index 85dcff104936..80c52e06b4ce 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
@@ -579,13 +579,13 @@ &cpsw3g {
 
 &cpsw_port1 {
 	bootph-all;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	status = "okay";
 };
 
 &cpsw_port2 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy3>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
index 1fb1b91a1bad..34bfa99bd4b8 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
@@ -499,13 +499,13 @@ &cpsw3g {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	status = "okay";
 };
 
 &cpsw_port2 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy1>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
index 8f64d6272b1b..e5f2f20fdb11 100644
--- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
+++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
@@ -185,7 +185,7 @@ &cpsw3g {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 0c42c486d83a..961287b6a3ed 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -586,7 +586,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
index b697035df04e..5255e04b9ac7 100644
--- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
+++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
@@ -249,7 +249,7 @@ cpsw3g_phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
index 41c8f8526e15..edc9f9b12f0e 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
@@ -281,7 +281,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
index adef02bd8040..911007778bc6 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
@@ -175,7 +175,7 @@ phy1: ethernet-phy@0 {
 
 &main_cpsw_port1 {
 	phy-handle = <&phy1>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
index 75a107456ce1..b8400cba832b 100644
--- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
@@ -705,7 +705,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 	bootph-all;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
index 5896e57b5b9e..3a870b9b984d 100644
--- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
@@ -771,7 +771,7 @@ mcu_phy0: ethernet-phy@0 {
 
 &mcu_cpsw_port1 {
 	status = "okay";
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&mcu_phy0>;
 	bootph-all;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index f684ce6ad9ad..4608828512d1 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -334,7 +334,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
index 352fb60e6ce8..2e9455ab0bfa 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
@@ -677,7 +677,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 45311438315f..317cd0bfa406 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -780,7 +780,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
index f84aa9f94547..3bfe6036a8e6 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
@@ -37,7 +37,7 @@ &rgmii3_default_pins
 &cpsw0_port1 {
 	status = "okay";
 	phy-handle = <&cpsw9g_phy12>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	mac-address = [00 00 00 00 00 00];
 	phys = <&cpsw0_phy_gmii_sel 1>;
 };
@@ -45,7 +45,7 @@ &cpsw0_port1 {
 &cpsw0_port2 {
 	status = "okay";
 	phy-handle = <&cpsw9g_phy15>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	mac-address = [00 00 00 00 00 00];
 	phys = <&cpsw0_phy_gmii_sel 2>;
 };
@@ -53,7 +53,7 @@ &cpsw0_port2 {
 &cpsw0_port3 {
 	status = "okay";
 	phy-handle = <&cpsw9g_phy0>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	mac-address = [00 00 00 00 00 00];
 	phys = <&cpsw0_phy_gmii_sel 3>;
 };
@@ -61,7 +61,7 @@ &cpsw0_port3 {
 &cpsw0_port4 {
 	status = "okay";
 	phy-handle = <&cpsw9g_phy3>;
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	mac-address = [00 00 00 00 00 00];
 	phys = <&cpsw0_phy_gmii_sel 4>;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
index 5e5784ef6f85..febbac9262de 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
@@ -1045,7 +1045,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 9e43dcff8ef2..24f57f02588f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -469,7 +469,7 @@ phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&phy0>;
 };
 
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
index 8583178fa1f3..6869a95c6214 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
@@ -80,6 +80,6 @@ main_cpsw_phy0: ethernet-phy@0 {
 
 &main_cpsw_port1 {
 	status = "okay";
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&main_cpsw_phy0>;
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index e0e303da7e15..5e7767e45130 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -388,7 +388,7 @@ cpsw3g_phy0: ethernet-phy@0 {
 };
 
 &cpsw_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&cpsw3g_phy0>;
 	status = "okay";
 	bootph-all;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
index 419c1a70e028..4221f172779b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
@@ -920,7 +920,7 @@ mcu_phy0: ethernet-phy@0 {
 
 &mcu_cpsw_port1 {
 	status = "okay";
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&mcu_phy0>;
 };
 
@@ -944,7 +944,7 @@ main_cpsw1_phy0: ethernet-phy@0 {
 };
 
 &main_cpsw1_port1 {
-	phy-mode = "rgmii-rxid";
+	phy-mode = "rgmii-id";
 	phy-handle = <&main_cpsw1_phy0>;
 	status = "okay";
 };
-- 
2.51.0

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Vignesh Raghavendra]

+ Francesco, Wadim, Daniel, Matthias

Please test/review

Hi Siddharth,

On 25/10/25 13:07, Siddharth Vadapalli wrote:
> The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> correction has been implemented/enforced by the updates to:
> a) Device-Tree binding for CPSW [0]
> b) Driver for CPSW [1]
> c) Driver for CPSW MAC Port's GMII [2]
> 
> To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> 'rgmii-id'.
> 
> [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> 
> Hello,
> 
> This patch is based on linux-next tagged next-20251024.


What boards have been tested?

[...]


-- 
Regards
Vignesh
https://ti.com/opensource

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Siddharth Vadapalli]

On Mon, 2025-11-03 at 09:30 +0530, Vignesh Raghavendra wrote:

Hello Vignesh,

> + Francesco, Wadim, Daniel, Matthias
> 
> Please test/review
> 
> Hi Siddharth,
> 
> On 25/10/25 13:07, Siddharth Vadapalli wrote:
> > The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> > CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> > correction has been implemented/enforced by the updates to:
> > a) Device-Tree binding for CPSW [0]
> > b) Driver for CPSW [1]
> > c) Driver for CPSW MAC Port's GMII [2]
> > 
> > To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> > 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> > 'rgmii-id'.
> > 
> > [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> > [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> > [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > 
> > Hello,
> > 
> > This patch is based on linux-next tagged next-20251024.
> 
> 
> What boards have been tested?

The following is the list of boards on which the patch has been tested,
along with the test logs:

1. AM62A7-SK:
https://gist.github.com/Siddharth-Vadapalli-at-TI/7952f349fa9654fe5ff1cc6bf660ad8b
2. AM62P5-SK:
https://gist.github.com/Siddharth-Vadapalli-at-TI/cf3671be887d57f20ca1c2cb7f094650
3. AM642-EVM:
https://gist.github.com/Siddharth-Vadapalli-at-TI/b02f8f4a2e05aba1235a000746690311
4. AM68-SK:
https://gist.github.com/Siddharth-Vadapalli-at-TI/146b8ba5eaf654f19a3cbdd4dd36bb36
5. AM69-SK:
https://gist.github.com/Siddharth-Vadapalli-at-TI/090f410bb3cb6f0dbd2be527434c60bf
6. J7200-COMMON-PROCESSOR-BOARD:
https://gist.github.com/Siddharth-Vadapalli-at-TI/24bc3c30876e3ed7dc8f53ed8d7b7035
7. J721E-COMMON-PROCESSOR-BOARD:
https://gist.github.com/Siddharth-Vadapalli-at-TI/4e026303613a48656b512a84ad830253
8. J721S2-EVM:
https://gist.github.com/Siddharth-Vadapalli-at-TI/40b202bf50468bd724a14c5e896f8706
9. J722S-EVM:
https://gist.github.com/Siddharth-Vadapalli-at-TI/fe5523e384ba3e10b3d82c6d743b9665
10. J742S2-EVM:
https://gist.github.com/Siddharth-Vadapalli-at-TI/7d46156a9d3d101153d0efcdaccf1a4a
11. J784S4-EVM:
https://gist.github.com/Siddharth-Vadapalli-at-TI/8b9146d66e00f80af661c8cb4a90acfa

Regards,
Siddharth.

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Matthias Schiffer]

On Sat, 2025-10-25 at 13:07 +0530, Siddharth Vadapalli wrote:
> The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> correction has been implemented/enforced by the updates to:
> a) Device-Tree binding for CPSW [0]
> b) Driver for CPSW [1]
> c) Driver for CPSW MAC Port's GMII [2]
> 
> To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> 'rgmii-id'.
> 
> [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> 
> Hello,
> 
> This patch is based on linux-next tagged next-20251024.
> 
> Regards,
> Siddharth.

Tested-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com> # k3-am642-tqma64xxl-mbax4xxl


> 
>  arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi          | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi           | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi           | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi               | 2 +-
>  arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts           | 2 +-
>  arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi           | 3 +--
>  arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi         | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62a7-sk.dts                  | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi          | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi          | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi              | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62p5-sk.dts                  | 4 ++--
>  arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi       | 2 +-
>  arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi           | 2 +-
>  arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi          | 2 +-
>  arch/arm64/boot/dts/ti/k3-am642-evm.dts                  | 4 ++--
>  arch/arm64/boot/dts/ti/k3-am642-sk.dts                   | 4 ++--
>  arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts   | 2 +-
>  arch/arm64/boot/dts/ti/k3-am654-base-board.dts           | 2 +-
>  arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts           | 2 +-
>  arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts         | 2 +-
>  arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi          | 2 +-
>  arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts         | 2 +-
>  arch/arm64/boot/dts/ti/k3-am69-sk.dts                    | 2 +-
>  arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts    | 2 +-
>  arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts       | 2 +-
>  arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts    | 2 +-
>  arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso  | 8 ++++----
>  arch/arm64/boot/dts/ti/k3-j721e-sk.dts                   | 2 +-
>  arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts   | 2 +-
>  arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso | 2 +-
>  arch/arm64/boot/dts/ti/k3-j722s-evm.dts                  | 2 +-
>  arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi  | 4 ++--
>  33 files changed, 40 insertions(+), 41 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> index eeca643fedbe..985963774c00 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi
> @@ -214,7 +214,7 @@ &cpsw3g {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy1>;
>  	bootph-all;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
> index 5c1284b802ad..3d1406acf680 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-dev.dtsi
> @@ -74,7 +74,7 @@ &cpsw_port1 {
>  /* Verdin ETH_2_RGMII */
>  &cpsw_port2 {
>  	phy-handle = <&cpsw3g_phy1>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
> index 71c29eab0eee..844f59f772e1 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin-ivy.dtsi
> @@ -268,7 +268,7 @@ &cpsw_port1 {
>  /* Verdin ETH_2_RGMII */
>  &cpsw_port2 {
>  	phy-handle = <&cpsw3g_phy1>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
> index dc4b228a9fd7..2a7242a2fef8 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi
> @@ -845,7 +845,7 @@ &cpsw3g {
>  /* Verdin ETH_1 (On-module PHY) */
>  &cpsw_port1 {
>  	phy-handle = <&cpsw3g_phy0>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "disabled";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
> index 7028d9835c4a..7b9ae467e95a 100644
> --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts
> @@ -593,7 +593,7 @@ &cpsw3g {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
> index fe0b98e1d105..7eb9066bff82 100644
> --- a/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am625-sk-common.dtsi
> @@ -215,8 +215,7 @@ &cpsw3g {
>  };
>  
>  &cpsw_port2 {
> -	/* PCB provides an internal delay of 2ns */
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy1>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
> index b3d012a5a26a..b24a63feeab8 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62a-phycore-som.dtsi
> @@ -192,7 +192,7 @@ &cpsw3g {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy1>;
>  	bootph-all;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> index af591fe6ae4f..de850307912c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts
> @@ -731,7 +731,7 @@ &phy_gmii_sel {
>  
>  &cpsw_port1 {
>  	status = "okay";
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	bootph-all;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
> index 0679d76f31bd..a0d5b15fc147 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-dev.dtsi
> @@ -78,7 +78,7 @@ &cpsw_port1 {
>  /* Verdin ETH_2_RGMII */
>  &cpsw_port2 {
>  	phy-handle = <&carrier_eth_phy>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
> index 317c8818f9ee..04f13edcb166 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin-ivy.dtsi
> @@ -275,7 +275,7 @@ &cpsw_port1 {
>  /* Verdin ETH_2_RGMII */
>  &cpsw_port2 {
>  	phy-handle = <&carrier_eth_phy>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
> index 99810047614e..5e050cbb9eaf 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi
> @@ -813,7 +813,7 @@ som_eth_phy: ethernet-phy@0 {
>  /* Verdin ETH_1 (On-module PHY) */
>  &cpsw_port1 {
>  	phy-handle = <&som_eth_phy>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "disabled";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> index a064a632680e..f04cf2d23d84 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
> @@ -541,14 +541,14 @@ &cpsw3g {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	status = "okay";
>  	bootph-all;
>  };
>  
>  &cpsw_port2 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy1>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
> index aab74d6019b0..d6e70ee15938 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62x-phyboard-lyra.dtsi
> @@ -291,7 +291,7 @@ &cpsw3g {
>  };
>  
>  &cpsw_port2 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy3>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
> index 58f78c0de292..50ed859ae06c 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi
> @@ -438,7 +438,7 @@ &cpsw3g {
>  
>  &cpsw_port1 {
>  	bootph-all;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> index 02ef1dd92eaa..d64fb81b04e2 100644
> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
> @@ -178,7 +178,7 @@ cpsw3g_phy1: ethernet-phy@1 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy1>;
>  	bootph-all;
>  	status = "okay";
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> index 85dcff104936..80c52e06b4ce 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts
> @@ -579,13 +579,13 @@ &cpsw3g {
>  
>  &cpsw_port1 {
>  	bootph-all;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	status = "okay";
>  };
>  
>  &cpsw_port2 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy3>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> index 1fb1b91a1bad..34bfa99bd4b8 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts
> @@ -499,13 +499,13 @@ &cpsw3g {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	status = "okay";
>  };
>  
>  &cpsw_port2 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy1>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> index 8f64d6272b1b..e5f2f20fdb11 100644
> --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl-mbax4xxl.dts
> @@ -185,7 +185,7 @@ &cpsw3g {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> index 0c42c486d83a..961287b6a3ed 100644
> --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
> @@ -586,7 +586,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
> index b697035df04e..5255e04b9ac7 100644
> --- a/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am67a-beagley-ai.dts
> @@ -249,7 +249,7 @@ cpsw3g_phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	status = "okay";
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
> index 41c8f8526e15..edc9f9b12f0e 100644
> --- a/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am68-phyboard-izar.dts
> @@ -281,7 +281,7 @@ J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
> index adef02bd8040..911007778bc6 100644
> --- a/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am68-phycore-som.dtsi
> @@ -175,7 +175,7 @@ phy1: ethernet-phy@0 {
>  
>  &main_cpsw_port1 {
>  	phy-handle = <&phy1>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	status = "okay";
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> index 75a107456ce1..b8400cba832b 100644
> --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts
> @@ -705,7 +705,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  	bootph-all;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> index 5896e57b5b9e..3a870b9b984d 100644
> --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts
> @@ -771,7 +771,7 @@ mcu_phy0: ethernet-phy@0 {
>  
>  &mcu_cpsw_port1 {
>  	status = "okay";
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&mcu_phy0>;
>  	bootph-all;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> index f684ce6ad9ad..4608828512d1 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
> @@ -334,7 +334,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> index 352fb60e6ce8..2e9455ab0bfa 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts
> @@ -677,7 +677,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> index 45311438315f..317cd0bfa406 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
> @@ -780,7 +780,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
> index f84aa9f94547..3bfe6036a8e6 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-gesi-exp-board.dtso
> @@ -37,7 +37,7 @@ &rgmii3_default_pins
>  &cpsw0_port1 {
>  	status = "okay";
>  	phy-handle = <&cpsw9g_phy12>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	mac-address = [00 00 00 00 00 00];
>  	phys = <&cpsw0_phy_gmii_sel 1>;
>  };
> @@ -45,7 +45,7 @@ &cpsw0_port1 {
>  &cpsw0_port2 {
>  	status = "okay";
>  	phy-handle = <&cpsw9g_phy15>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	mac-address = [00 00 00 00 00 00];
>  	phys = <&cpsw0_phy_gmii_sel 2>;
>  };
> @@ -53,7 +53,7 @@ &cpsw0_port2 {
>  &cpsw0_port3 {
>  	status = "okay";
>  	phy-handle = <&cpsw9g_phy0>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	mac-address = [00 00 00 00 00 00];
>  	phys = <&cpsw0_phy_gmii_sel 3>;
>  };
> @@ -61,7 +61,7 @@ &cpsw0_port3 {
>  &cpsw0_port4 {
>  	status = "okay";
>  	phy-handle = <&cpsw9g_phy3>;
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	mac-address = [00 00 00 00 00 00];
>  	phys = <&cpsw0_phy_gmii_sel 4>;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> index 5e5784ef6f85..febbac9262de 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> @@ -1045,7 +1045,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> index 9e43dcff8ef2..24f57f02588f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
> @@ -469,7 +469,7 @@ phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&phy0>;
>  };
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> index 8583178fa1f3..6869a95c6214 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-evm-gesi-exp-board.dtso
> @@ -80,6 +80,6 @@ main_cpsw_phy0: ethernet-phy@0 {
>  
>  &main_cpsw_port1 {
>  	status = "okay";
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&main_cpsw_phy0>;
>  };
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> index e0e303da7e15..5e7767e45130 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
> @@ -388,7 +388,7 @@ cpsw3g_phy0: ethernet-phy@0 {
>  };
>  
>  &cpsw_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&cpsw3g_phy0>;
>  	status = "okay";
>  	bootph-all;
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> index 419c1a70e028..4221f172779b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-evm-common.dtsi
> @@ -920,7 +920,7 @@ mcu_phy0: ethernet-phy@0 {
>  
>  &mcu_cpsw_port1 {
>  	status = "okay";
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&mcu_phy0>;
>  };
>  
> @@ -944,7 +944,7 @@ main_cpsw1_phy0: ethernet-phy@0 {
>  };
>  
>  &main_cpsw1_port1 {
> -	phy-mode = "rgmii-rxid";
> +	phy-mode = "rgmii-id";
>  	phy-handle = <&main_cpsw1_phy0>;
>  	status = "okay";
>  };

-- 
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Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Francesco Dolcini]

On Sat, Oct 25, 2025 at 01:07:59PM +0530, Siddharth Vadapalli wrote:
> The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> correction has been implemented/enforced by the updates to:
> a) Device-Tree binding for CPSW [0]
> b) Driver for CPSW [1]
> c) Driver for CPSW MAC Port's GMII [2]
> 
> To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> 'rgmii-id'.
> 
> [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Tested-by: Francesco Dolcini <francesco.dolcini@toradex.com> # Toradex Verdin AM62P

Verdin AM62 is the same regarding ethernet, so I expect no issue also
there.

Francesco

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Vignesh Raghavendra]

Hi Siddharth Vadapalli,

On Sat, 25 Oct 2025 13:07:59 +0530, Siddharth Vadapalli wrote:
> The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> correction has been implemented/enforced by the updates to:
> a) Device-Tree binding for CPSW [0]
> b) Driver for CPSW [1]
> c) Driver for CPSW MAC Port's GMII [2]
> 
> [...]

I have applied the following to branch ti-k3-dts-next on [1].
Thank you!

[1/1] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports
      commit: 1446fc4dc0728328904e8cb402f065bcc905bcec

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Vignesh

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Francesco Dolcini]

+Tom +U-Boot ML

Hello Siddharth,

On Sat, Oct 25, 2025 at 01:07:59PM +0530, Siddharth Vadapalli wrote:
> The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> correction has been implemented/enforced by the updates to:
> a) Device-Tree binding for CPSW [0]
> b) Driver for CPSW [1]
> c) Driver for CPSW MAC Port's GMII [2]
> 
> To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> 'rgmii-id'.
> 
> [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")

What about U-Boot?
I just noticed this in today U-Boot master:

  RGMII mode without internal TX delay unsupported; please fix your Device Tree

and I think this is coming from the DTS update from Linux to U-Boot.

Can you look into that?

Francesco

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Francesco Dolcini]

On Mon, Jan 12, 2026 at 08:49:56AM +0100, Francesco Dolcini wrote:
> +Tom +U-Boot ML
> 
> Hello Siddharth,
> 
> On Sat, Oct 25, 2025 at 01:07:59PM +0530, Siddharth Vadapalli wrote:
> > The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> > CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> > correction has been implemented/enforced by the updates to:
> > a) Device-Tree binding for CPSW [0]
> > b) Driver for CPSW [1]
> > c) Driver for CPSW MAC Port's GMII [2]
> > 
> > To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> > 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> > 'rgmii-id'.
> > 
> > [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> > [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> > [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> 
> What about U-Boot?
> I just noticed this in today U-Boot master:
> 
>   RGMII mode without internal TX delay unsupported; please fix your Device Tree
> 
> and I think this is coming from the DTS update from Linux to U-Boot.
> 
> Can you look into that?

Ok, I think that the issue is that the U-Boot code was updated
correctly, but now we need the v6.19 DT in U-Boot, and as of now we have
6.18 DT.

Tom: are you planning to sync the U-Boot DT to Linux v6.19 before the next
U-Boot release?


Francesco

Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Tom Rini]

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On Mon, Jan 12, 2026 at 08:56:36AM +0100, Francesco Dolcini wrote:
> On Mon, Jan 12, 2026 at 08:49:56AM +0100, Francesco Dolcini wrote:
> > +Tom +U-Boot ML
> > 
> > Hello Siddharth,
> > 
> > On Sat, Oct 25, 2025 at 01:07:59PM +0530, Siddharth Vadapalli wrote:
> > > The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> > > CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> > > correction has been implemented/enforced by the updates to:
> > > a) Device-Tree binding for CPSW [0]
> > > b) Driver for CPSW [1]
> > > c) Driver for CPSW MAC Port's GMII [2]
> > > 
> > > To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> > > 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> > > 'rgmii-id'.
> > > 
> > > [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> > > [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> > > [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> > 
> > What about U-Boot?
> > I just noticed this in today U-Boot master:
> > 
> >   RGMII mode without internal TX delay unsupported; please fix your Device Tree
> > 
> > and I think this is coming from the DTS update from Linux to U-Boot.
> > 
> > Can you look into that?
> 
> Ok, I think that the issue is that the U-Boot code was updated
> correctly, but now we need the v6.19 DT in U-Boot, and as of now we have
> 6.18 DT.
> 
> Tom: are you planning to sync the U-Boot DT to Linux v6.19 before the next
> U-Boot release?

Once it's out, yes. But, uh, this tells me some TI folks forgot to
backport all of the dts changes too then as we shouldn't have broken
platforms in-tree like this.

-- 
Tom

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Re: [PATCH] arm64: dts: ti: k3-*: Replace rgmii-rxid with rgmii-id for CPSW ports

[Siddharth Vadapalli]

On Mon, 2026-01-12 at 12:06 -0600, Tom Rini wrote:
> On Mon, Jan 12, 2026 at 08:56:36AM +0100, Francesco Dolcini wrote:
> > On Mon, Jan 12, 2026 at 08:49:56AM +0100, Francesco Dolcini wrote:
> > > +Tom +U-Boot ML
> > > 
> > > Hello Siddharth,
> > > 
> > > On Sat, Oct 25, 2025 at 01:07:59PM +0530, Siddharth Vadapalli wrote:
> > > > The MAC Ports across all of the CPSW instances (CPSW2G, CPSW3G, CPSW5G and
> > > > CPSW9G) present in various K3 SoCs only support the 'RGMII-ID' mode. This
> > > > correction has been implemented/enforced by the updates to:
> > > > a) Device-Tree binding for CPSW [0]
> > > > b) Driver for CPSW [1]
> > > > c) Driver for CPSW MAC Port's GMII [2]
> > > > 
> > > > To complete the transition from 'RGMII-RXID' to 'RGMII-ID', update the
> > > > 'phy-mode' property for all CPSW ports by replacing 'rgmii-rxid' with
> > > > 'rgmii-id'.
> > > > 
> > > > [0]: commit 9b357ea52523 ("dt-bindings: net: ti: k3-am654-cpsw-nuss: update phy-mode in example")
> > > > [1]: commit ca13b249f291 ("net: ethernet: ti: am65-cpsw: fixup PHY mode for fixed RGMII TX delay")
> > > > [2]: commit a22d3b0d49d4 ("phy: ti: gmii-sel: Always write the RGMII ID setting")
> > > 
> > > What about U-Boot?
> > > I just noticed this in today U-Boot master:
> > > 
> > >   RGMII mode without internal TX delay unsupported; please fix your Device Tree
> > > 
> > > and I think this is coming from the DTS update from Linux to U-Boot.
> > > 
> > > Can you look into that?
> > 
> > Ok, I think that the issue is that the U-Boot code was updated
> > correctly, but now we need the v6.19 DT in U-Boot, and as of now we have
> > 6.18 DT.
> > 
> > Tom: are you planning to sync the U-Boot DT to Linux v6.19 before the next
> > U-Boot release?
> 
> Once it's out, yes. But, uh, this tells me some TI folks forgot to
> backport all of the dts changes too then as we shouldn't have broken
> platforms in-tree like this.

In both Linux and U-Boot, the error (warning) message:
    RGMII mode without internal TX delay unsupported; please fix your
Device Tree
only indicates that the device-tree should be updated to use 'rgmii-id'
instead of 'rgmii-rxid'. The functionality however remains unaffected. The
current Linux device-tree patch is not really fixing an issue from a
functionality perspective, and the same holds true for U-Boot.

I realize however that a DT sync patch could (should) have been posted by
me to the U-Boot mailing list after this patch had been merged to Linux
instead of waiting for the periodic DT sync.

Regards,
Siddharth.