Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu

[Conor Dooley <conor@kernel.org>]

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On Sat, Nov 08, 2025 at 03:48:18PM +0100, Krzysztof Kozlowski wrote:
> On 08/11/2025 15:47, Krzysztof Kozlowski wrote:
> > On 08/11/2025 14:59, revy wrote:
> >>
> >>
> >>
> >>> -----Original Messages-----
> >>> From: "Krzysztof Kozlowski" <krzk@kernel.org>
> >>> Sent Time: 2025-11-08 19:29:07 (Saturday)
> >>> To: gaohan@iscas.ac.cn, "Paul Walmsley" <pjw@kernel.org>, "Palmer Dabbelt" <palmer@dabbelt.com>, "Albert Ou" <aou@eecs.berkeley.edu>, "Alexandre Ghiti" <alex@ghiti.fr>, "Rob Herring" <robh@kernel.org>, "Krzysztof Kozlowski" <krzk+dt@kernel.org>, "Conor Dooley" <conor+dt@kernel.org>, "Chen-Yu Tsai" <wens@csie.org>, "Jernej Skrabec" <jernej.skrabec@gmail.com>, "Samuel Holland" <samuel@sholland.org>, "Yixun Lan" <dlan@gentoo.org>, "Drew Fustini" <fustini@kernel.org>, "Geert Uytterhoeven" <geert+renesas@glider.be>, "Guodong Xu" <guodong@riscstar.com>, "Haylen Chu" <heylenay@4d2.org>, "Joel Stanley" <joel@jms.id.au>
> >>> Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, "Han Gao" <rabenda.cn@gmail.com>
> >>> Subject: Re: [PATCH 1/3] riscv: soc: re-organized allwinner menu
> >>>
> >>> On 08/11/2025 09:20, gaohan@iscas.ac.cn wrote:
> >>>> From: Han Gao <gaohan@iscas.ac.cn>
> >>>>
> >>>> Allwinner currently offers d1(s)/v821/v861/v881 on RISC-V,
> >>>> using different IPs.
> >>>>
> >>>> d1(s): Xuantie C906
> >>>> v821: Andes A27 + XuanTie E907
> >>>> v861/v881: XuanTie C907
> >>>>
> >>>> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>
> >>>> ---
> >>>> arch/riscv/Kconfig.socs | 22 +++++++++++++++++-----
> >>>> 1 file changed, 17 insertions(+), 5 deletions(-)
> >>>>
> >>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
> >>>> index 848e7149e443..7cba5d6ec4c3 100644
> >>>> --- a/arch/riscv/Kconfig.socs
> >>>> +++ b/arch/riscv/Kconfig.socs
> >>>> @@ -54,14 +54,26 @@ config SOC_STARFIVE
> >>>> 	help
> >>>> 	  This enables support for StarFive SoC platform hardware.
> >>>>
> >>>> -config ARCH_SUNXI
> >>>> -	bool "Allwinner sun20i SoCs"
> >>>> +menuconfig ARCH_SUNXI
> >>>> +	bool "Allwinner RISC-V SoCs"
> >>>> +
> >>>> +if ARCH_SUNXI
> >>>> +
> >>>> +config ARCH_SUNXI_XUANTIE
> >>>
> >>>
> >>> You should not get multiple ARCHs. ARCH is only one. There is also not
> >>> much rationale in commit msg for that.
> >>
> >> The main goal is to avoid choosing multiple IP addresses for erreta. 
> >> If using Andes IPs, I don't want to choose XuanTIe (T-Head) ERRETA.
> > 
> > Not explained in commit msg but anyway not a good argument. It is some
> > sort of micro optimization and you completely miss the point we target
> > multiarch kernels.
> 
> Heh, and I actually did not forbid or discourage choosing erratas per
> your soc. I said you only get one top level ARCH. Look at all arm64
> platforms. How many ARCHs are there per one vendor?


Yeah, it only allows you to enable the errata, it doesn't force any of
them to "y". Some will get enabled by default when ARCH_SUNXI is
enabled, but if someone is only targeting on device they can just turn
them off... I'm pretty inclined to just NAK this unless there's some
actual value.

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