From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A348ACCFA13 for ; Sun, 9 Nov 2025 17:16:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Owner; bh=Ge5/bHgLrWdI1igXKXsfuN228hZbyVzznmmpCnqu1bI=; b=YlHiGbc0owIV/KV/A6s42+2Ysp NYsi2nB+iuQpfqhgR9fhu7KQTdl4KCAY8gAtG8VpAliMPNRsB+Hn8HibVOT59ojJLwE+RoqpxgehC FDffDD5AoESpwoH8bnpOXo56qtaMNm7wpf6OqbtQ2hvxzY9lN8jY40rZvbSC7Qhk0RCAW8Q3Otg1g k3EccCfzwEeVgIS8qFjwdIJRTq0ROHqZiylEuexpFc+ItTf8GBenocnoQOffaSrhwVJFA6mMdc3i8 S78pwD91ZiyCDMNlhf1h3fDhNmgp27LzYvL1SYoskyqinEaVZMGUrsFQQkSelm+BA89haIbQseyrr 7bax6RGQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vI91k-00000004CAI-3UIu; Sun, 09 Nov 2025 17:16:32 +0000 Received: from tor.source.kernel.org ([172.105.4.254]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vI91j-00000004C92-1zN1 for linux-arm-kernel@lists.infradead.org; Sun, 09 Nov 2025 17:16:31 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 8091F60007; Sun, 9 Nov 2025 17:16:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28D55C4CEF7; Sun, 9 Nov 2025 17:16:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762708590; bh=LU5ZFdx4EUgvb0p/xCvsj9L4R5ggGs+NLiMz5m9HfUc=; h=From:To:Cc:Subject:Date:From; b=sFhLtFYG3Z+0+DBLaN0LKpKwk6ur3WVl9zuRVWr+46ey1p8gnSk5u84BNs3sDaDIE xdxfHpDB6jXpaFnestxrxmSbo2SH6uT0tb39tuZ/bqdinwzFXQezUHtMcnkuIBrsJG sBRNdRp8+1bfyr/uS5NkAICDk/7HrUhatH/4LUS791pDgy4X5N6+vSELUJOt3xqHLL ppFpYzfLxGH7bM7u9xwpxv/FENRGsy5LoTRk5f8tVl54DyXNYGZvdWaYdaZapLZnqH 7KY/1aX8n3+lfVefc4tTGgb73zfXyfq+x76oXQoA6LQ1Lt0y6neYjIRroarqRGNKbZ E7RqSzBrRLYSA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vI91f-00000003exw-3VIj; Sun, 09 Nov 2025 17:16:27 +0000 From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Christoffer Dall , Volodymyr Babchuk , Yao Yuan Subject: [PATCH v2 00/45] KVM: arm64: Add LR overflow infrastructure Date: Sun, 9 Nov 2025 17:15:34 +0000 Message-ID: <20251109171619.1507205-1-maz@kernel.org> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, christoffer.dall@arm.com, Volodymyr_Babchuk@epam.com, yaoyuan@linux.alibaba.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This is the 2nd version of the series originally posted at [1]. The series has significantly evolved with a bunch of bug fixes, some additional optimisations, and a number of test cases. This has now been extensively tested on much of what I have access to, specially on some of the most broken stuff (Apple, Qualcomm, Cavium, ARMv8.0 CPUs without TDIR), but also on some less shitty systems (which are the minority, unsurprisingly). Given that this is fixing some really ugly vgic bugs, I'm aiming this at 6.19, though these bugs being 10 year old, any form of urgency is very questionable. Patches still against -rc4. * From v1 [1]: - Fixed the ICH_HCR_EL2.TDIR detection code to include the Apple stuff, and to deal with GICv5's legacy mode - Fixed compilation issue for old toolchains that don't understand the GICv3 sysreg names - Allow GICv3 in-LR deactivation even when DIR trapping is enabled - Dropped the split overflow list, once I convinced myself it wasn't bringing much to the table - Turned kvm_vgic_vcpu_enable() into a vgic reset helper - Remove IPI-ing on GICv3 systems without TDIR - Fixed the out-of-LR deactivation when dealing with asymmetric SPI deactivation - Fixed broken MMIO offset computation - Added group enable to the GIC selftest library - Added fixes and improvements to the vgic_irq selftest: - Fixed definition of spurious interrupt - Fixed config/enable ordering - Prevent timer interrupts from being injected from userspace - Removed limit of 4 interrupts being injected at any given time - Added an asymmetric SPI deactivation test case - Added a Group-0 enable test case - Added a timer interrupt + SPI interrupt test case - Fixed a couple of spelling mistakes (and added many more, I'm sure) - Reordered the series slightly [1] https://lore.kernel.org/r/20251103165517.2960148-1-maz@kernel.org Marc Zyngier (45): irqchip/gic: Add missing GICH_HCR control bits irqchip/gic: Expose CPU interface VA to KVM irqchip/apple-aic: Spit out ICH_MISR_EL2 value on spurious vGIC MI KVM: arm64: Turn vgic-v3 errata traps into a patched-in constant KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping KVM: arm64: Repack struct vgic_irq fields KVM: arm64: Add tracking of vgic_irq being present in a LR KVM: arm64: Add LR overflow handling documentation KVM: arm64: GICv3: Drop LPI active state when folding LRs KVM: arm64: GICv3: Preserve EOIcount on exit KVM: arm64: GICv3: Decouple ICH_HCR_EL2 programming from LRs KVM: arm64: GICv3: Extract LR folding primitive KVM: arm64: GICv3: Extract LR computing primitive KVM: arm64: GICv2: Preserve EOIcount on exit KVM: arm64: GICv2: Decouple GICH_HCR programming from LRs being loaded KVM: arm64: GICv2: Extract LR folding primitive KVM: arm64: GICv2: Extract LR computing primitive KVM: arm64: Compute vgic state irrespective of the number of interrupts KVM: arm64: Eagerly save VMCR on exit KVM: arm64: Revamp vgic maintenance interrupt configuration KVM: arm64: Turn kvm_vgic_vcpu_enable() into kvm_vgic_vcpu_reset() KVM: arm64: Make vgic_target_oracle() globally available KVM: arm64: Invert ap_list sorting to push active interrupts out KVM: arm64: Move undeliverable interrupts to the end of ap_list KVM: arm64: Use MI to detect groups being enabled/disabled KVM: arm64: GICv3: Handle LR overflow when EOImode==0 KVM: arm64: GICv3: Handle deactivation via ICV_DIR_EL1 traps KVM: arm64: GICv3: Add GICv2 SGI handling to deactivation primitive KVM: arm64: GICv3: Set ICH_HCR_EL2.TDIR when interrupts overflow LR capacity KVM: arm64: GICv3: Add SPI tracking to handle asymmetric deactivation KVM: arm64: GICv3: Handle in-LR deactivation when possible KVM: arm64: GICv3: Avoid broadcast kick on CPUs lacking TDIR KVM: arm64: GICv2: Handle LR overflow when EOImode==0 KVM: arm64: GICv2: Handle deactivation via GICV_DIR traps KVM: arm64: GICv2: Always trap GICV_DIR register KVM: arm64: selftests: gic_v3: Add irq group setting helper KVM: arm64: selftests: gic_v3: Disable Group-0 interrupts by default KVM: arm64: selftests: vgic_irq: Fix GUEST_ASSERT_IAR_EMPTY() helper KVM: arm64: selftests: vgic_irq: Change configuration before enabling interrupt KVM: arm64: selftests: vgic_irq: Exclude timer-controlled interrupts KVM: arm64: selftests: vgic_irq: Remove LR-bound limitation KVM: arm64: selftests: vgic_irq: Perform EOImode==1 deactivation in ack order KVM: arm64: selftests: vgic_irq: Add asymmetric SPI deaectivation test KVM: arm64: selftests: vgic_irq: Add Group-0 enable test KVM: arm64: selftests: vgic_irq: Add timer deactivation test arch/arm64/include/asm/kvm_asm.h | 2 +- arch/arm64/include/asm/kvm_host.h | 1 + arch/arm64/include/asm/kvm_hyp.h | 2 +- arch/arm64/include/asm/virt.h | 7 +- arch/arm64/kernel/cpufeature.c | 52 +++ arch/arm64/kernel/hyp-stub.S | 5 + arch/arm64/kernel/image-vars.h | 1 + arch/arm64/kvm/arm.c | 7 +- arch/arm64/kvm/hyp/nvhe/hyp-main.c | 7 +- arch/arm64/kvm/hyp/vgic-v2-cpuif-proxy.c | 4 + arch/arm64/kvm/hyp/vgic-v3-sr.c | 87 ++-- arch/arm64/kvm/sys_regs.c | 19 +- arch/arm64/kvm/vgic/vgic-init.c | 9 +- arch/arm64/kvm/vgic/vgic-mmio-v2.c | 24 + arch/arm64/kvm/vgic/vgic-mmio.h | 1 + arch/arm64/kvm/vgic/vgic-v2.c | 291 +++++++++--- arch/arm64/kvm/vgic/vgic-v3-nested.c | 11 +- arch/arm64/kvm/vgic/vgic-v3.c | 421 ++++++++++++++---- arch/arm64/kvm/vgic/vgic-v4.c | 5 +- arch/arm64/kvm/vgic/vgic.c | 294 +++++++----- arch/arm64/kvm/vgic/vgic.h | 42 +- arch/arm64/tools/cpucaps | 1 + drivers/irqchip/irq-apple-aic.c | 7 +- drivers/irqchip/irq-gic.c | 3 + include/kvm/arm_vgic.h | 29 +- include/linux/irqchip/arm-gic.h | 6 + include/linux/irqchip/arm-vgic-info.h | 2 + tools/testing/selftests/kvm/arm64/vgic_irq.c | 285 +++++++++++- .../testing/selftests/kvm/include/arm64/gic.h | 1 + tools/testing/selftests/kvm/lib/arm64/gic.c | 6 + .../selftests/kvm/lib/arm64/gic_private.h | 1 + .../testing/selftests/kvm/lib/arm64/gic_v3.c | 17 + 32 files changed, 1276 insertions(+), 374 deletions(-) -- 2.47.3