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From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
	kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Oliver Upton <oupton@kernel.org>,
	Zenghui Yu <yuzenghui@huawei.com>,
	Christoffer Dall <christoffer.dall@arm.com>,
	Volodymyr Babchuk <Volodymyr_Babchuk@epam.com>,
	Yao Yuan <yaoyuan@linux.alibaba.com>
Subject: [PATCH v2 20/45] KVM: arm64: Revamp vgic maintenance interrupt configuration
Date: Sun,  9 Nov 2025 17:15:54 +0000	[thread overview]
Message-ID: <20251109171619.1507205-21-maz@kernel.org> (raw)
In-Reply-To: <20251109171619.1507205-1-maz@kernel.org>

We currently don't use the maintenance interrupt very much, apart
from EOI on level interrupts, and for LR underflow in limited cases.

However, as we are moving toward a setup where active interrupts
can live outside of the LRs, we need to use the MIs in a more
diverse set of cases.

Add a new helper that produces a digest of the ap_list, and use
that summary to set the various control bits as required.

This slightly changes the way v2 SGIs are handled, as they used to
count for more than one interrupt, but not anymore.

Signed-off-by: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/kvm/vgic/vgic-v2.c | 12 ++++-
 arch/arm64/kvm/vgic/vgic-v3.c | 15 +++++-
 arch/arm64/kvm/vgic/vgic.c    | 91 ++++++++++++-----------------------
 arch/arm64/kvm/vgic/vgic.h    | 19 +++++++-
 4 files changed, 71 insertions(+), 66 deletions(-)

diff --git a/arch/arm64/kvm/vgic/vgic-v2.c b/arch/arm64/kvm/vgic/vgic-v2.c
index 07e93acafd04d..f53bc55288978 100644
--- a/arch/arm64/kvm/vgic/vgic-v2.c
+++ b/arch/arm64/kvm/vgic/vgic-v2.c
@@ -26,11 +26,19 @@ void vgic_v2_init_lrs(void)
 		vgic_v2_write_lr(i, 0);
 }
 
-void vgic_v2_set_underflow(struct kvm_vcpu *vcpu)
+void vgic_v2_configure_hcr(struct kvm_vcpu *vcpu,
+			   struct ap_list_summary *als)
 {
 	struct vgic_v2_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v2;
 
-	cpuif->vgic_hcr |= GICH_HCR_UIE;
+	cpuif->vgic_hcr = GICH_HCR_EN;
+
+	if (irqs_pending_outside_lrs(als))
+		cpuif->vgic_hcr |= GICH_HCR_NPIE;
+	if (irqs_active_outside_lrs(als))
+		cpuif->vgic_hcr |= GICH_HCR_LRENPIE;
+	if (irqs_outside_lrs(als))
+		cpuif->vgic_hcr |= GICH_HCR_UIE;
 }
 
 static bool lr_signals_eoi_mi(u32 lr_val)
diff --git a/arch/arm64/kvm/vgic/vgic-v3.c b/arch/arm64/kvm/vgic/vgic-v3.c
index 2619e120484c5..d23db8f7b450a 100644
--- a/arch/arm64/kvm/vgic/vgic-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-v3.c
@@ -20,11 +20,22 @@ static bool common_trap;
 static bool dir_trap;
 static bool gicv4_enable;
 
-void vgic_v3_set_underflow(struct kvm_vcpu *vcpu)
+void vgic_v3_configure_hcr(struct kvm_vcpu *vcpu,
+			   struct ap_list_summary *als)
 {
 	struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3;
 
-	cpuif->vgic_hcr |= ICH_HCR_EL2_UIE;
+	cpuif->vgic_hcr = ICH_HCR_EL2_En;
+
+	if (irqs_pending_outside_lrs(als))
+		cpuif->vgic_hcr |= ICH_HCR_EL2_NPIE;
+	if (irqs_active_outside_lrs(als))
+		cpuif->vgic_hcr |= ICH_HCR_EL2_LRENPIE;
+	if (irqs_outside_lrs(als))
+		cpuif->vgic_hcr |= ICH_HCR_EL2_UIE;
+
+	if (!als->nr_sgi)
+		cpuif->vgic_hcr |= ICH_HCR_EL2_vSGIEOICount;
 }
 
 static bool lr_signals_eoi_mi(u64 lr_val)
diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
index 46b31cd365466..c420f8262e4c1 100644
--- a/arch/arm64/kvm/vgic/vgic.c
+++ b/arch/arm64/kvm/vgic/vgic.c
@@ -791,38 +791,30 @@ static inline void vgic_clear_lr(struct kvm_vcpu *vcpu, int lr)
 		vgic_v3_clear_lr(vcpu, lr);
 }
 
-static inline void vgic_set_underflow(struct kvm_vcpu *vcpu)
-{
-	if (kvm_vgic_global_state.type == VGIC_V2)
-		vgic_v2_set_underflow(vcpu);
-	else
-		vgic_v3_set_underflow(vcpu);
-}
-
-/* Requires the ap_list_lock to be held. */
-static int compute_ap_list_depth(struct kvm_vcpu *vcpu,
-				 bool *multi_sgi)
+static void summarize_ap_list(struct kvm_vcpu *vcpu,
+			      struct ap_list_summary *als)
 {
 	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
 	struct vgic_irq *irq;
-	int count = 0;
-
-	*multi_sgi = false;
 
 	lockdep_assert_held(&vgic_cpu->ap_list_lock);
 
-	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
-		int w;
+	*als = (typeof(*als)){};
 
-		raw_spin_lock(&irq->irq_lock);
-		/* GICv2 SGIs can count for more than one... */
-		w = vgic_irq_get_lr_count(irq);
-		raw_spin_unlock(&irq->irq_lock);
+	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
+		scoped_guard(raw_spinlock, &irq->irq_lock) {
+			if (vgic_target_oracle(irq) != vcpu)
+				continue;
+
+			if (!irq->active)
+				als->nr_pend++;
+			else
+				als->nr_act++;
+		}
 
-		count += w;
-		*multi_sgi |= (w > 1);
+		if (irq->intid < VGIC_NR_SGIS)
+			als->nr_sgi++;
 	}
-	return count;
 }
 
 /*
@@ -908,60 +900,39 @@ static int compute_ap_list_depth(struct kvm_vcpu *vcpu,
 static void vgic_flush_lr_state(struct kvm_vcpu *vcpu)
 {
 	struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
+	struct ap_list_summary als;
 	struct vgic_irq *irq;
-	int count;
-	bool multi_sgi;
-	u8 prio = 0xff;
-	int i = 0;
+	int count = 0;
 
 	lockdep_assert_held(&vgic_cpu->ap_list_lock);
 
-	count = compute_ap_list_depth(vcpu, &multi_sgi);
-	if (count > kvm_vgic_global_state.nr_lr || multi_sgi)
-		vgic_sort_ap_list(vcpu);
+	summarize_ap_list(vcpu, &als);
 
-	count = 0;
+	if (irqs_outside_lrs(&als))
+		vgic_sort_ap_list(vcpu);
 
 	list_for_each_entry(irq, &vgic_cpu->ap_list_head, ap_list) {
-		raw_spin_lock(&irq->irq_lock);
-
-		/*
-		 * If we have multi-SGIs in the pipeline, we need to
-		 * guarantee that they are all seen before any IRQ of
-		 * lower priority. In that case, we need to filter out
-		 * these interrupts by exiting early. This is easy as
-		 * the AP list has been sorted already.
-		 */
-		if (multi_sgi && irq->priority > prio) {
-			raw_spin_unlock(&irq->irq_lock);
-			break;
+		scoped_guard(raw_spinlock,  &irq->irq_lock) {
+			if (likely(vgic_target_oracle(irq) == vcpu)) {
+				vgic_populate_lr(vcpu, irq, count++);
+			}
 		}
 
-		if (likely(vgic_target_oracle(irq) == vcpu)) {
-			vgic_populate_lr(vcpu, irq, count++);
-
-			if (irq->source)
-				prio = irq->priority;
-		}
-
-		raw_spin_unlock(&irq->irq_lock);
-
-		if (count == kvm_vgic_global_state.nr_lr) {
-			if (!list_is_last(&irq->ap_list,
-					  &vgic_cpu->ap_list_head))
-				vgic_set_underflow(vcpu);
+		if (count == kvm_vgic_global_state.nr_lr)
 			break;
-		}
 	}
 
 	/* Nuke remaining LRs */
-	for (i = count ; i < kvm_vgic_global_state.nr_lr; i++)
+	for (int i = count ; i < kvm_vgic_global_state.nr_lr; i++)
 		vgic_clear_lr(vcpu, i);
 
-	if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif))
+	if (!static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif)) {
 		vcpu->arch.vgic_cpu.vgic_v2.used_lrs = count;
-	else
+		vgic_v2_configure_hcr(vcpu, &als);
+	} else {
 		vcpu->arch.vgic_cpu.vgic_v3.used_lrs = count;
+		vgic_v3_configure_hcr(vcpu, &als);
+	}
 }
 
 static inline bool can_access_vgic_from_kernel(void)
diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h
index 0ecadfa00397d..4a0733869cb5f 100644
--- a/arch/arm64/kvm/vgic/vgic.h
+++ b/arch/arm64/kvm/vgic/vgic.h
@@ -236,6 +236,21 @@ struct its_ite {
 	u32 event_id;
 };
 
+struct ap_list_summary {
+	unsigned int	nr_pend;	/* purely pending, not active */
+	unsigned int	nr_act;		/* active, or active+pending */
+	unsigned int	nr_sgi;		/* any SGI */
+};
+
+#define irqs_outside_lrs(s)						\
+	 (((s)->nr_pend + (s)->nr_act) > kvm_vgic_global_state.nr_lr)
+
+#define irqs_pending_outside_lrs(s)			\
+	((s)->nr_pend > kvm_vgic_global_state.nr_lr)
+
+#define irqs_active_outside_lrs(s)		\
+	((s)->nr_act &&	irqs_outside_lrs(s))
+
 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 		       struct vgic_reg_attr *reg_attr);
 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
@@ -262,7 +277,7 @@ int vgic_check_iorange(struct kvm *kvm, phys_addr_t ioaddr,
 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
-void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
+void vgic_v2_configure_hcr(struct kvm_vcpu *vcpu, struct ap_list_summary *als);
 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 			 int offset, u32 *val);
@@ -302,7 +317,7 @@ static inline void vgic_get_irq_ref(struct vgic_irq *irq)
 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
-void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
+void vgic_v3_configure_hcr(struct kvm_vcpu *vcpu, struct ap_list_summary *als);
 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 void vgic_v3_enable(struct kvm_vcpu *vcpu);
-- 
2.47.3



  parent reply	other threads:[~2025-11-09 17:17 UTC|newest]

Thread overview: 83+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-09 17:15 [PATCH v2 00/45] KVM: arm64: Add LR overflow infrastructure Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 01/45] irqchip/gic: Add missing GICH_HCR control bits Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 02/45] irqchip/gic: Expose CPU interface VA to KVM Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 03/45] irqchip/apple-aic: Spit out ICH_MISR_EL2 value on spurious vGIC MI Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 04/45] KVM: arm64: Turn vgic-v3 errata traps into a patched-in constant Marc Zyngier
2025-11-10 10:40   ` Suzuki K Poulose
2025-11-10 11:47     ` Marc Zyngier
2025-11-11 23:53   ` Oliver Upton
2025-11-13  9:52   ` Marek Szyprowski
2025-11-13 10:56     ` Marc Zyngier
2025-11-13 11:04       ` Marek Szyprowski
2025-11-13 11:23         ` Joey Gouly
2025-11-13 11:42           ` Marc Zyngier
2025-11-13 10:59     ` Marc Zyngier
2025-11-13 11:20       ` Marek Szyprowski
2025-11-13 18:01   ` Mark Brown
2025-11-14  9:37     ` Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 05/45] KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping Marc Zyngier
2025-11-13 14:33   ` Mark Brown
2025-11-13 18:15     ` Marc Zyngier
2025-11-13 19:06       ` Mark Brown
2025-11-13 20:10         ` Marc Zyngier
2025-11-13 21:59           ` Oliver Upton
2025-11-09 17:15 ` [PATCH v2 06/45] KVM: arm64: Repack struct vgic_irq fields Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 07/45] KVM: arm64: Add tracking of vgic_irq being present in a LR Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 08/45] KVM: arm64: Add LR overflow handling documentation Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 09/45] KVM: arm64: GICv3: Drop LPI active state when folding LRs Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 10/45] KVM: arm64: GICv3: Preserve EOIcount on exit Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 11/45] KVM: arm64: GICv3: Decouple ICH_HCR_EL2 programming from LRs Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 12/45] KVM: arm64: GICv3: Extract LR folding primitive Marc Zyngier
2025-11-10  9:01   ` Yao Yuan
2025-11-10  9:18     ` Marc Zyngier
2025-11-10  9:48       ` Yao Yuan
2025-11-09 17:15 ` [PATCH v2 13/45] KVM: arm64: GICv3: Extract LR computing primitive Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 14/45] KVM: arm64: GICv2: Preserve EOIcount on exit Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 15/45] KVM: arm64: GICv2: Decouple GICH_HCR programming from LRs being loaded Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 16/45] KVM: arm64: GICv2: Extract LR folding primitive Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 17/45] KVM: arm64: GICv2: Extract LR computing primitive Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 18/45] KVM: arm64: Compute vgic state irrespective of the number of interrupts Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 19/45] KVM: arm64: Eagerly save VMCR on exit Marc Zyngier
2025-11-09 17:15 ` Marc Zyngier [this message]
2025-11-12  0:08   ` [PATCH v2 20/45] KVM: arm64: Revamp vgic maintenance interrupt configuration Oliver Upton
2025-11-12  8:33     ` Marc Zyngier
2025-11-12  8:45       ` Oliver Upton
2025-11-12  9:56         ` Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 21/45] KVM: arm64: Turn kvm_vgic_vcpu_enable() into kvm_vgic_vcpu_reset() Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 22/45] KVM: arm64: Make vgic_target_oracle() globally available Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 23/45] KVM: arm64: Invert ap_list sorting to push active interrupts out Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 24/45] KVM: arm64: Move undeliverable interrupts to the end of ap_list Marc Zyngier
2025-11-09 17:15 ` [PATCH v2 25/45] KVM: arm64: Use MI to detect groups being enabled/disabled Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 26/45] KVM: arm64: GICv3: Handle LR overflow when EOImode==0 Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 27/45] KVM: arm64: GICv3: Handle deactivation via ICV_DIR_EL1 traps Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 28/45] KVM: arm64: GICv3: Add GICv2 SGI handling to deactivation primitive Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 29/45] KVM: arm64: GICv3: Set ICH_HCR_EL2.TDIR when interrupts overflow LR capacity Marc Zyngier
2025-11-14 14:20   ` Fuad Tabba
2025-11-14 15:02     ` Marc Zyngier
2025-11-14 15:53       ` Fuad Tabba
2025-11-14 17:41         ` Marc Zyngier
2025-11-17  8:22           ` Fuad Tabba
2025-11-17 11:56             ` Marc Zyngier
2025-11-24 11:52       ` Mark Brown
2025-11-24 13:06         ` Marc Zyngier
2025-11-24 13:23           ` Mark Brown
2025-11-24 13:40             ` Marc Zyngier
2025-11-24 14:12               ` Marc Zyngier
2025-11-24 15:06                 ` Mark Brown
2025-11-09 17:16 ` [PATCH v2 30/45] KVM: arm64: GICv3: Add SPI tracking to handle asymmetric deactivation Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 31/45] KVM: arm64: GICv3: Handle in-LR deactivation when possible Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 32/45] KVM: arm64: GICv3: Avoid broadcast kick on CPUs lacking TDIR Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 33/45] KVM: arm64: GICv2: Handle LR overflow when EOImode==0 Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 34/45] KVM: arm64: GICv2: Handle deactivation via GICV_DIR traps Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 35/45] KVM: arm64: GICv2: Always trap GICV_DIR register Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 36/45] KVM: arm64: selftests: gic_v3: Add irq group setting helper Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 37/45] KVM: arm64: selftests: gic_v3: Disable Group-0 interrupts by default Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 38/45] KVM: arm64: selftests: vgic_irq: Fix GUEST_ASSERT_IAR_EMPTY() helper Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 39/45] KVM: arm64: selftests: vgic_irq: Change configuration before enabling interrupt Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 40/45] KVM: arm64: selftests: vgic_irq: Exclude timer-controlled interrupts Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 41/45] KVM: arm64: selftests: vgic_irq: Remove LR-bound limitation Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 42/45] KVM: arm64: selftests: vgic_irq: Perform EOImode==1 deactivation in ack order Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 43/45] KVM: arm64: selftests: vgic_irq: Add asymmetric SPI deaectivation test Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 44/45] KVM: arm64: selftests: vgic_irq: Add Group-0 enable test Marc Zyngier
2025-11-09 17:16 ` [PATCH v2 45/45] KVM: arm64: selftests: vgic_irq: Add timer deactivation test Marc Zyngier
2025-11-12  9:13 ` [PATCH v2 00/45] KVM: arm64: Add LR overflow infrastructure Oliver Upton

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