From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74985CCFA1A for ; Tue, 11 Nov 2025 10:51:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=kR1q3vSE4f3+9HuAT86eVdE7RRrhxVddnTODqQHRZmM=; b=KFxGarS4apQx1T28l9Wa30i9Du ejBE+PwgDR54fFXtfB8kHLgjlpTgJPzSXlYFKvIXtcxJ1M53Ldpm0xZ46PTqndLvKH0KN0gZ7wSle rb740dIFNncvdcFN5pOjRZoMxFup9SwjWDOcXsYy6tHOyWOrpx8nfOHyJn80hUJ7CTbtUK5nTiyYI I2B5N9WwXdyvnioV/lc5rh8+R/zrN58uwBabYdzH20OoTOvMV+dIaecpuPEmrXODQsevW5OBy0Nkp bZ2cSIcsbHXLZxYjr/WAHVhqiDSQ7r9M8FhMo4MlRNepU58PcZOojFqQTgTSaEX/Xrjb7OjDagkQ+ d4udvIqQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vIly4-00000006znV-2qDx; Tue, 11 Nov 2025 10:51:20 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.98.2 #2 (Red Hat Linux)) id 1vIly2-00000006zmp-2a6J; Tue, 11 Nov 2025 10:51:18 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id B915861916; Tue, 11 Nov 2025 10:51:16 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 83466C19423; Tue, 11 Nov 2025 10:51:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762858276; bh=rbd6HJp7KfiGzI6RAUTXMzl0OF+lOVMXVO/KlmeFA2c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cbqzXw3rf2X7ThmuWlTZ6Ms6X0onVCl521gTTlUTVOgTY8G0gp5FAcygHqoqldUyO Y7cGb3yB1D0CKpXMwfUYMBwwESwqHvkjM/YiYeoB17lnlNG728PaKhf9EkJNkDq+qm InA90OGip8bTt6yXQLtE2/hwZGCO9t/3wzh+kQgngIu43/OKZQi93n0NZ7bfE3pocZ m7LcaFouKhN+n+paRvehC352UvRO/iPfRUkMk5YK9wxlJveNlVK9fCS5ZH1Rrqw0Hp d7AFT0GvxyQt1FGRFKeh53ag//fVsbhLS6wCetmYdxS/vp3BslFiHp289vqgniYc9o MOOq78jZz/82A== From: Niklas Cassel To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner Cc: Shawn Lin , FUKAUMI Naoki , Krishna chaitanya chundru , Niklas Cassel , stable@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: [PATCH 1/6] Revert "PCI: dw-rockchip: Don't wait for link since we can detect Link Up" Date: Tue, 11 Nov 2025 11:51:01 +0100 Message-ID: <20251111105100.869997-9-cassel@kernel.org> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251111105100.869997-8-cassel@kernel.org> References: <20251111105100.869997-8-cassel@kernel.org> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3523; i=cassel@kernel.org; h=from:subject; bh=rbd6HJp7KfiGzI6RAUTXMzl0OF+lOVMXVO/KlmeFA2c=; b=owGbwMvMwCV2MsVw8cxjvkWMp9WSGDKFRUXPH1vBY3v5R9H2rJkRF1ffWcJ46cRl3RbTvSY/b IPMN6W97yhlYRDjYpAVU2Tx/eGyv7jbfcpxxTs2MHNYmUCGMHBxCsBErtcz/Hesu3WwtPvGL43A gqyp779VXj1XpNRkE17UeOXSVb7iek6G/xm332WvizuZkl3Qanzd/fz5XRpenVGHPluYPa7akb9 MmgkA X-Developer-Key: i=cassel@kernel.org; a=openpgp; fpr=5ADE635C0E631CBBD5BE065A352FE6582ED9B5DA Content-Transfer-Encoding: 8bit X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This reverts commit ec9fd499b9c60a187ac8d6414c3c343c77d32e42. While this fake hotplugging was a nice idea, it has shown that this feature does not handle PCIe switches correctly: pci_bus 0004:43: busn_res: can not insert [bus 43-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci_bus 0004:43: busn_res: [bus 43-41] end is updated to 43 pci_bus 0004:43: busn_res: can not insert [bus 43] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci 0004:42:00.0: devices behind bridge are unusable because [bus 43] cannot be assigned for them pci_bus 0004:44: busn_res: can not insert [bus 44-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci_bus 0004:44: busn_res: [bus 44-41] end is updated to 44 pci_bus 0004:44: busn_res: can not insert [bus 44] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci 0004:42:02.0: devices behind bridge are unusable because [bus 44] cannot be assigned for them pci_bus 0004:45: busn_res: can not insert [bus 45-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci_bus 0004:45: busn_res: [bus 45-41] end is updated to 45 pci_bus 0004:45: busn_res: can not insert [bus 45] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci 0004:42:06.0: devices behind bridge are unusable because [bus 45] cannot be assigned for them pci_bus 0004:46: busn_res: can not insert [bus 46-41] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci_bus 0004:46: busn_res: [bus 46-41] end is updated to 46 pci_bus 0004:46: busn_res: can not insert [bus 46] under [bus 42-41] (conflicts with (null) [bus 42-41]) pci 0004:42:0e.0: devices behind bridge are unusable because [bus 46] cannot be assigned for them pci_bus 0004:42: busn_res: [bus 42-41] end is updated to 46 pci_bus 0004:42: busn_res: can not insert [bus 42-46] under [bus 41] (conflicts with (null) [bus 41]) pci 0004:41:00.0: devices behind bridge are unusable because [bus 42-46] cannot be assigned for them pcieport 0004:40:00.0: bridge has subordinate 41 but max busn 46 During the initial scan, PCI core doesn't see the switch and since the Root Port is not hot plug capable, the secondary bus number gets assigned as the subordinate bus number. This means, the PCI core assumes that only one bus will appear behind the Root Port since the Root Port is not hot plug capable. This works perfectly fine for PCIe endpoints connected to the Root Port, since they don't extend the bus. However, if a PCIe switch is connected, then there is a problem when the downstream busses starts showing up and the PCI core doesn't extend the subordinate bus number after initial scan during boot. The long term plan is to migrate this driver to the pwrctrl framework, once it adds proper support for powering up and enumerating PCIe switches. Cc: stable@vger.kernel.org Suggested-by: Manivannan Sadhasivam Signed-off-by: Niklas Cassel --- drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 3e2752c7dd09..07378ececd88 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -541,7 +541,6 @@ static int rockchip_pcie_configure_rc(struct platform_device *pdev, pp = &rockchip->pci.pp; pp->ops = &rockchip_pcie_host_ops; - pp->use_linkup_irq = true; ret = dw_pcie_host_init(pp); if (ret) { -- 2.51.1