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Wed, 12 Nov 2025 07:22:34 -0800 (PST) Received: from ho-tower-lan.lan ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42ac677ab75sm33573485f8f.35.2025.11.12.07.22.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 12 Nov 2025 07:22:34 -0800 (PST) From: James Clark Date: Wed, 12 Nov 2025 15:22:12 +0000 Subject: [PATCH v4 06/13] coresight: Interpret ETMv3 config with ATTR_CFG_GET_FLD() MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251112-james-cs-syncfreq-v4-6-165ba21401dc@linaro.org> References: <20251112-james-cs-syncfreq-v4-0-165ba21401dc@linaro.org> In-Reply-To: <20251112-james-cs-syncfreq-v4-0-165ba21401dc@linaro.org> To: Suzuki K Poulose , Mike Leach , Alexander Shishkin , Jonathan Corbet , Leo Yan Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, James Clark X-Mailer: b4 0.14.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251112_072236_360624_042CE14B X-CRM114-Status: GOOD ( 18.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently we're programming attr->config directly into ETMCR after some validation. This obscures which fields are being used, and also makes it impossible to move fields around or use other configN fields in the future. Improve it by only reading the fields that are valid and then setting the appropriate ETMCR bits based on each one. The ETMCR_CTXID_SIZE part can be removed as it was never a valid option because it's not in ETM3X_SUPPORTED_OPTIONS. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-etm3x-core.c | 24 ++++++++++++---------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c index a5e809589d3e..4511fc2f8d72 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "coresight-etm.h" @@ -339,21 +340,22 @@ static int etm_parse_event_config(struct etm_drvdata *drvdata, if (attr->config & ~ETM3X_SUPPORTED_OPTIONS) return -EINVAL; - config->ctrl = attr->config; + config->ctrl = 0; - /* Don't trace contextID when runs in non-root PID namespace */ - if (!task_is_in_init_pid_ns(current)) - config->ctrl &= ~ETMCR_CTXID_SIZE; + if (ATTR_CFG_GET_FLD(attr, cycacc)) + config->ctrl |= ETMCR_CYC_ACC; + + if (ATTR_CFG_GET_FLD(attr, timestamp)) + config->ctrl |= ETMCR_TIMESTAMP_EN; /* - * Possible to have cores with PTM (supports ret stack) and ETM - * (never has ret stack) on the same SoC. So if we have a request - * for return stack that can't be honoured on this core then - * clear the bit - trace will still continue normally + * Possible to have cores with PTM (supports ret stack) and ETM (never + * has ret stack) on the same SoC. So only enable when it can be honored + * - trace will still continue normally otherwise. */ - if ((config->ctrl & ETMCR_RETURN_STACK) && - !(drvdata->etmccer & ETMCCER_RETSTACK)) - config->ctrl &= ~ETMCR_RETURN_STACK; + if (ATTR_CFG_GET_FLD(attr, retstack) && + (drvdata->etmccer & ETMCCER_RETSTACK)) + config->ctrl |= ETMCR_RETURN_STACK; return 0; } -- 2.34.1