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(unknown [172.20.64.188]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id CA62C41C017B; Mon, 17 Nov 2025 09:59:44 +0800 (CST) From: Jun Guo To: peter.chen@cixtech.com, fugang.duan@cixtech.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, robin.murphy@arm.com Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, Jun Guo Subject: [PATCH 2/3] dma: arm-dma350: add support for shared interrupt mode Date: Mon, 17 Nov 2025 09:59:42 +0800 Message-Id: <20251117015943.2858-3-jun.guo@cixtech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251117015943.2858-1-jun.guo@cixtech.com> References: <20251117015943.2858-1-jun.guo@cixtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CD:EE_|SG2PR06MB5336:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 3d916844-b3fa-4193-764e-08de257cfb88 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|7416014|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AanZ1OEgoZjSVDBpBky33+HtgEgyMpBbkBvtTI2cXtEL3Z3mhI6Vf7+FHeLp?= =?us-ascii?Q?mQVCo8DnZaZCKAPGRl1OnlG0Xpo1UmEcQmXtaQGZvS3ehE2UI4rhp2iiX6Z2?= =?us-ascii?Q?oSscFq0J5B16Tdteicd+CahuzlOK+MkhjQWWdE1yc+Rwh0miRgnG+paCv+Rm?= =?us-ascii?Q?65uN1zPHf/vC03rtOSQWGVofo5cgt8h9r4we/JPE+dc+qX8Wc4IgKDJeeHAV?= =?us-ascii?Q?CemFfeinv2VkZUGuyMHfWyJDhRZVhxJVtgi3Sfd3m3buhhJCNKk+iVxv+oNl?= =?us-ascii?Q?M9I0IUwckBOQoL9TJZXoqv9y8DlJbhhQP3ldrmAgrgirCj/l4EPHX2PriSFj?= =?us-ascii?Q?fYo7r4NE4848pq5FKN2WbQTkeq2sdtfEbU1z3LH4RRlwXKYJlKuBRBdFGqDW?= =?us-ascii?Q?IyhRsf2Hl6T9JxSf0e9j2eO+G5FdO9pOEEDKKHYwx/toXwbv6KIMPwGvjvy5?= =?us-ascii?Q?ojy26y0io2yD/TTsu0LvvPjhdVshDzNxr3hRtq8npHmcjDXajJ2GFD08r0gn?= =?us-ascii?Q?Nls30TuNIzJnSJvdbGi/+spSCEkav+WXYCT6AdiHXarkkdP/DRUiLN012a7n?= =?us-ascii?Q?Uybdn1VN+tAhylCyblq5kg68f3lVSF2AkITKIEvAPFe9voX4Y2XD8UgYLulB?= =?us-ascii?Q?t/3YD2IkJlunTPrMKnstL4BD9AH4BZswUdmFUdkxWfvS4hIywI++3GDVR7cz?= =?us-ascii?Q?T5V0kGtuYPkTwfpwaXOja5RBLvSfLFCbX66BT8cRn9phPbCLQGK35gNypyTd?= =?us-ascii?Q?nbmohGhHP/BsWstjoZvZFXbMxyQILpOvhKb1jWFs2UukBM4FepTxsna5uouA?= =?us-ascii?Q?Sq4GCbb6pqGmF7XYSIh0ebqQPHfTCECmoZouoe3WIToO8qJ1b+qb5Nt+PJtG?= =?us-ascii?Q?4xjXz6EQ3GI9XX7V7pgIGJouc5f/lfGEldRzaSX6nzVszBIwpcfcZKlq142K?= =?us-ascii?Q?2zTRTGfsg1Z91xasDKP2OJCo0fUPnRN5fiQtyBhAdryDO6FCdxUHH1vQmO3X?= =?us-ascii?Q?sTLCCMLHJggc13A0S395DUWVKlcK9rBU3HRPV7nUzSWMbPBtJVS4i9AkmfWX?= =?us-ascii?Q?Vg5i8yJYNX7DUZw8jdx9LpfmLFgnUBevv6BWmrYGeK2HMgP3lKY31/rAki1N?= =?us-ascii?Q?Qlek5XvkXv5am5eh4NpIEOLd75WokxI9yTnYsa2x1UFZxD/8njhVsqXODs/h?= =?us-ascii?Q?qkJnd8+/SylR/L6/qioe5sEN6BvBiLTtOS1ZilA15rzJ1bjfE97Wma3QMafr?= =?us-ascii?Q?W7TUcQbDDZIBxNitzULUQCa0d8iaBf3GB5ZSA+BQqNC6XEl2PvteqBTr7nah?= =?us-ascii?Q?FdE85wBlKGn3Y1rTKTtBARvNaUaIFKKEdkpch1iSiIVDdf/SR1eLjLmGXuNe?= =?us-ascii?Q?54mFO7+psC0XDHGMsP+JeN0rU3q+PgfUFKfYkLJ/HrhCae7N5CY/U3SLnkGH?= =?us-ascii?Q?f1Rphe3C2qHJrlzF2zG19zntIvm8M1TBeDONFsV/TxSjhDryYiPQfCJnqgec?= =?us-ascii?Q?yUyLLgo+8MTyD84UxJSR1o44SpT9iEjmUDdT2TNsiFhXk6nePWL0Rbk9J9Kv?= =?us-ascii?Q?zVg4tesdqLAM8sA6DJY=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(7416014)(376014)(1800799024)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Nov 2025 01:59:45.7674 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d916844-b3fa-4193-764e-08de257cfb88 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CD.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SG2PR06MB5336 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251116_175955_929242_F4861C1A X-CRM114-Status: GOOD ( 23.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org - The arm dma350 controller's hardware implementation varies: some designs dedicate a separate interrupt line for each channel, while others have all channels sharing a single interrupt.This patch adds support for the hardware design where all DMA channels share a single interrupt. Signed-off-by: Jun Guo --- drivers/dma/arm-dma350.c | 115 +++++++++++++++++++++++++++++++++++---- 1 file changed, 105 insertions(+), 10 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 9efe2ca7d5ec..cb1907be18d0 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -14,6 +14,7 @@ #include "virt-dma.h" #define DMAINFO 0x0f00 +#define DRIVER_NAME "arm-dma350" #define DMA_BUILDCFG0 0xb0 #define DMA_CFG_DATA_WIDTH GENMASK(18, 16) @@ -142,6 +143,9 @@ #define LINK_LINKADDR BIT(30) #define LINK_LINKADDRHI BIT(31) +/* DMA NONSECURE CONTROL REGISTER */ +#define DMANSECCTRL 0x20c +#define INTREN_ANYCHINTR_EN BIT(0) enum ch_ctrl_donetype { CH_CTRL_DONETYPE_NONE = 0, @@ -192,6 +196,7 @@ struct d350_chan { struct d350 { struct dma_device dma; + void __iomem *base; int nchan; int nreq; struct d350_chan channels[] __counted_by(nchan); @@ -461,7 +466,61 @@ static void d350_issue_pending(struct dma_chan *chan) spin_unlock_irqrestore(&dch->vc.lock, flags); } -static irqreturn_t d350_irq(int irq, void *data) +static irqreturn_t d350_global_irq(int irq, void *data) +{ + struct d350 *dmac = (struct d350 *)data; + struct device *dev = dmac->dma.dev; + irqreturn_t ret = IRQ_NONE; + int i; + + for (i = 0; i < dmac->nchan; i++) { + struct d350_chan *dch = &dmac->channels[i]; + u32 ch_status; + + ch_status = readl(dch->base + CH_STATUS); + if (!ch_status) + continue; + + ret = IRQ_HANDLED; + + if (ch_status & CH_STAT_INTR_ERR) { + struct virt_dma_desc *vd = &dch->desc->vd; + u32 errinfo = readl_relaxed(dch->base + CH_ERRINFO); + + if (errinfo & + (CH_ERRINFO_AXIRDPOISERR | CH_ERRINFO_AXIRDRESPERR)) + vd->tx_result.result = DMA_TRANS_READ_FAILED; + else if (errinfo & CH_ERRINFO_AXIWRRESPERR) + vd->tx_result.result = DMA_TRANS_WRITE_FAILED; + else + vd->tx_result.result = DMA_TRANS_ABORTED; + + vd->tx_result.residue = d350_get_residue(dch); + } else if (!(ch_status & CH_STAT_INTR_DONE)) { + dev_warn(dev, "Channel %d unexpected IRQ: 0x%08x\n", i, + ch_status); + } + + writel_relaxed(ch_status, dch->base + CH_STATUS); + + spin_lock(&dch->vc.lock); + if (ch_status & CH_STAT_INTR_DONE) { + vchan_cookie_complete(&dch->desc->vd); + dch->status = DMA_COMPLETE; + dch->residue = 0; + d350_start_next(dch); + } else if (ch_status & CH_STAT_INTR_ERR) { + vchan_cookie_complete(&dch->desc->vd); + dch->status = DMA_ERROR; + dch->residue = dch->desc->vd.tx_result.residue; + } + spin_unlock(&dch->vc.lock); + } + + return ret; +} + +static irqreturn_t d350_channel_irq(int irq, void *data) { struct d350_chan *dch = data; struct device *dev = dch->vc.chan.device->dev; @@ -506,10 +565,18 @@ static irqreturn_t d350_irq(int irq, void *data) static int d350_alloc_chan_resources(struct dma_chan *chan) { struct d350_chan *dch = to_d350_chan(chan); - int ret = request_irq(dch->irq, d350_irq, IRQF_SHARED, - dev_name(&dch->vc.chan.dev->device), dch); - if (!ret) - writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); + int ret = 0; + + if (dch->irq) { + ret = request_irq(dch->irq, d350_channel_irq, IRQF_SHARED, + dev_name(&dch->vc.chan.dev->device), dch); + if (ret) { + dev_err(chan->device->dev, "Failed to request IRQ %d\n", dch->irq); + return ret; + } + } + + writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); return ret; } @@ -526,7 +593,7 @@ static void d350_free_chan_resources(struct dma_chan *chan) static int d350_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct d350 *dmac; + struct d350 *dmac = NULL; void __iomem *base; u32 reg; int ret, nchan, dw, aw, r, p; @@ -556,6 +623,7 @@ static int d350_probe(struct platform_device *pdev) return -ENOMEM; dmac->nchan = nchan; + dmac->base = base; reg = readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); dmac->nreq = FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); @@ -582,6 +650,26 @@ static int d350_probe(struct platform_device *pdev) dmac->dma.device_issue_pending = d350_issue_pending; INIT_LIST_HEAD(&dmac->dma.channels); + /* Cix Sky1 has a common host IRQ for all its channels. */ + if (of_device_is_compatible(pdev->dev.of_node, "cix,sky1-dma-350")) { + int host_irq = platform_get_irq(pdev, 0); + + if (host_irq < 0) + return dev_err_probe(dev, host_irq, + "Failed to get IRQ\n"); + + ret = devm_request_irq(&pdev->dev, host_irq, d350_global_irq, + IRQF_SHARED, DRIVER_NAME, dmac); + if (ret) + return dev_err_probe( + dev, ret, + "Failed to request the combined IRQ %d\n", + host_irq); + + /* Combined Non-Secure Channel Interrupt Enable */ + writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL); + } + /* Would be nice to have per-channel caps for this... */ memset = true; for (int i = 0; i < nchan; i++) { @@ -595,10 +683,16 @@ static int d350_probe(struct platform_device *pdev) dev_warn(dev, "No command link support on channel %d\n", i); continue; } - dch->irq = platform_get_irq(pdev, i); - if (dch->irq < 0) - return dev_err_probe(dev, dch->irq, - "Failed to get IRQ for channel %d\n", i); + + if (!of_device_is_compatible(pdev->dev.of_node, + "cix,sky1-dma-350")) { + dch->irq = platform_get_irq(pdev, i); + if (dch->irq < 0) + return dev_err_probe( + dev, dch->irq, + "Failed to get IRQ for channel %d\n", + i); + } dch->has_wrap = FIELD_GET(CH_CFG_HAS_WRAP, reg); dch->has_trig = FIELD_GET(CH_CFG_HAS_TRIGIN, reg) & @@ -640,6 +734,7 @@ static void d350_remove(struct platform_device *pdev) } static const struct of_device_id d350_of_match[] __maybe_unused = { + { .compatible = "cix,sky1-dma-350" }, { .compatible = "arm,dma-350" }, {} }; -- 2.34.1