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From: Mostafa Saleh <smostafa@google.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,  kvmarm@lists.linux.dev,
	iommu@lists.linux.dev
Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
	 oliver.upton@linux.dev, joey.gouly@arm.com,
	suzuki.poulose@arm.com,  yuzenghui@huawei.com, joro@8bytes.org,
	jean-philippe@linaro.org, jgg@ziepe.ca,  praan@google.com,
	danielmentz@google.com, mark.rutland@arm.com,
	 qperret@google.com, tabba@google.com,
	Mostafa Saleh <smostafa@google.com>
Subject: [PATCH v5 09/27] KVM: arm64: iommu: Shadow host stage-2 page table
Date: Mon, 17 Nov 2025 18:47:56 +0000	[thread overview]
Message-ID: <20251117184815.1027271-10-smostafa@google.com> (raw)
In-Reply-To: <20251117184815.1027271-1-smostafa@google.com>

Create a shadow page table for the IOMMU that shadows the
host CPU stage-2 into the IOMMUs to establish DMA isolation.

An initial snapshot is created after the driver init, then
on every permission change a callback would be called for
the IOMMU driver to update the page table.

For some cases, an SMMUv3 may be able to share the same page
table used with the host CPU stage-2 directly.
However, this is too strict and requires changes to the core hypervisor
page table code, plus it would require the hypervisor to handle IOMMU
page faults. This can be added later as an optimization for SMMUV3.

Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
 arch/arm64/kvm/hyp/include/nvhe/iommu.h |  4 ++
 arch/arm64/kvm/hyp/nvhe/iommu/iommu.c   | 83 ++++++++++++++++++++++++-
 arch/arm64/kvm/hyp/nvhe/mem_protect.c   |  5 ++
 3 files changed, 90 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/hyp/include/nvhe/iommu.h b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
index 1ac70cc28a9e..219363045b1c 100644
--- a/arch/arm64/kvm/hyp/include/nvhe/iommu.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/iommu.h
@@ -3,11 +3,15 @@
 #define __ARM64_KVM_NVHE_IOMMU_H__
 
 #include <asm/kvm_host.h>
+#include <asm/kvm_pgtable.h>
 
 struct kvm_iommu_ops {
 	int (*init)(void);
+	void (*host_stage2_idmap)(phys_addr_t start, phys_addr_t end, int prot);
 };
 
 int kvm_iommu_init(void);
 
+void kvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
+				 enum kvm_pgtable_prot prot);
 #endif /* __ARM64_KVM_NVHE_IOMMU_H__ */
diff --git a/arch/arm64/kvm/hyp/nvhe/iommu/iommu.c b/arch/arm64/kvm/hyp/nvhe/iommu/iommu.c
index a01c036c55be..414bd4c97690 100644
--- a/arch/arm64/kvm/hyp/nvhe/iommu/iommu.c
+++ b/arch/arm64/kvm/hyp/nvhe/iommu/iommu.c
@@ -4,15 +4,94 @@
  *
  * Copyright (C) 2022 Linaro Ltd.
  */
+#include <linux/iommu.h>
+
 #include <nvhe/iommu.h>
+#include <nvhe/mem_protect.h>
+#include <nvhe/spinlock.h>
 
 /* Only one set of ops supported */
 struct kvm_iommu_ops *kvm_iommu_ops;
 
+/* Protected by host_mmu.lock */
+static bool kvm_idmap_initialized;
+
+static inline int pkvm_to_iommu_prot(enum kvm_pgtable_prot prot)
+{
+	int iommu_prot = 0;
+
+	if (prot & KVM_PGTABLE_PROT_R)
+		iommu_prot |= IOMMU_READ;
+	if (prot & KVM_PGTABLE_PROT_W)
+		iommu_prot |= IOMMU_WRITE;
+	if (prot == PKVM_HOST_MMIO_PROT)
+		iommu_prot |= IOMMU_MMIO;
+
+	/* We don't understand that, might be dangerous. */
+	WARN_ON(prot & ~PKVM_HOST_MEM_PROT);
+	return iommu_prot;
+}
+
+static int __snapshot_host_stage2(const struct kvm_pgtable_visit_ctx *ctx,
+				  enum kvm_pgtable_walk_flags visit)
+{
+	u64 start = ctx->addr;
+	kvm_pte_t pte = *ctx->ptep;
+	u32 level = ctx->level;
+	u64 end = start + kvm_granule_size(level);
+	int prot = IOMMU_READ | IOMMU_WRITE;
+
+	/* Keep unmapped. */
+	if (pte && !kvm_pte_valid(pte))
+		return 0;
+
+	if (kvm_pte_valid(pte))
+		prot = pkvm_to_iommu_prot(kvm_pgtable_stage2_pte_prot(pte));
+	else if (!addr_is_memory(start))
+		prot |= IOMMU_MMIO;
+
+	kvm_iommu_ops->host_stage2_idmap(start, end, prot);
+	return 0;
+}
+
+static int kvm_iommu_snapshot_host_stage2(void)
+{
+	int ret;
+	struct kvm_pgtable_walker walker = {
+		.cb	= __snapshot_host_stage2,
+		.flags	= KVM_PGTABLE_WALK_LEAF,
+	};
+	struct kvm_pgtable *pgt = &host_mmu.pgt;
+
+	hyp_spin_lock(&host_mmu.lock);
+	ret = kvm_pgtable_walk(pgt, 0, BIT(pgt->ia_bits), &walker);
+	/* Start receiving calls to host_stage2_idmap. */
+	kvm_idmap_initialized = !ret;
+	hyp_spin_unlock(&host_mmu.lock);
+
+	return ret;
+}
+
 int kvm_iommu_init(void)
 {
-	if (!kvm_iommu_ops || !kvm_iommu_ops->init)
+	int ret;
+
+	if (!kvm_iommu_ops || !kvm_iommu_ops->init ||
+	    !kvm_iommu_ops->host_stage2_idmap)
 		return -ENODEV;
 
-	return kvm_iommu_ops->init();
+	ret = kvm_iommu_ops->init();
+	if (ret)
+		return ret;
+	return kvm_iommu_snapshot_host_stage2();
+}
+
+void kvm_iommu_host_stage2_idmap(phys_addr_t start, phys_addr_t end,
+				 enum kvm_pgtable_prot prot)
+{
+	hyp_assert_lock_held(&host_mmu.lock);
+
+	if (!kvm_idmap_initialized)
+		return;
+	kvm_iommu_ops->host_stage2_idmap(start, end, pkvm_to_iommu_prot(prot));
 }
diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
index c3eac0da7cbe..f60acfb868d0 100644
--- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
+++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
@@ -15,6 +15,7 @@
 #include <hyp/fault.h>
 
 #include <nvhe/gfp.h>
+#include <nvhe/iommu.h>
 #include <nvhe/memory.h>
 #include <nvhe/mem_protect.h>
 #include <nvhe/mm.h>
@@ -529,6 +530,7 @@ static void __host_update_page_state(phys_addr_t addr, u64 size, enum pkvm_page_
 int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id)
 {
 	int ret;
+	enum kvm_pgtable_prot prot;
 
 	if (!range_is_memory(addr, addr + size))
 		return -EPERM;
@@ -538,6 +540,9 @@ int host_stage2_set_owner_locked(phys_addr_t addr, u64 size, u8 owner_id)
 	if (ret)
 		return ret;
 
+	prot = owner_id == PKVM_ID_HOST ? PKVM_HOST_MEM_PROT : 0;
+	kvm_iommu_host_stage2_idmap(addr, addr + size, prot);
+
 	/* Don't forget to update the vmemmap tracking for the host */
 	if (owner_id == PKVM_ID_HOST)
 		__host_update_page_state(addr, size, PKVM_PAGE_OWNED);
-- 
2.52.0.rc1.455.g30608eb744-goog



  parent reply	other threads:[~2025-11-17 18:49 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-17 18:47 [PATCH v5 00/27] KVM: arm64: SMMUv3 driver for pKVM (trap and emulate) Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 01/27] KVM: arm64: Add a new function to donate memory with prot Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 02/27] KVM: arm64: Donate MMIO to the hypervisor Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 03/27] KVM: arm64: pkvm: Add pkvm_time_get() Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 04/27] iommu/io-pgtable-arm: Factor kernel specific code out Mostafa Saleh
2025-11-28 16:45   ` Jason Gunthorpe
2025-12-12 15:37     ` Mostafa Saleh
2025-12-16  0:58       ` Jason Gunthorpe
2025-12-16 23:08         ` Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 05/27] iommu/arm-smmu-v3: Split code with hyp Mostafa Saleh
2025-11-28 16:46   ` Jason Gunthorpe
2025-12-12 15:41     ` Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 06/27] iommu/arm-smmu-v3: Move TLB range invalidation into common code Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 07/27] iommu/arm-smmu-v3: Move IDR parsing to common functions Mostafa Saleh
2025-11-28 16:48   ` Jason Gunthorpe
2025-12-12 15:42     ` Mostafa Saleh
2025-12-17 13:59       ` Jason Gunthorpe
2025-11-17 18:47 ` [PATCH v5 08/27] KVM: arm64: iommu: Introduce IOMMU driver infrastructure Mostafa Saleh
2025-11-17 18:47 ` Mostafa Saleh [this message]
2025-11-17 18:47 ` [PATCH v5 10/27] KVM: arm64: iommu: Add memory pool Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 11/27] KVM: arm64: iommu: Support DABT for IOMMU Mostafa Saleh
2025-11-17 18:47 ` [PATCH v5 12/27] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 13/27] iommu/arm-smmu-v3-kvm: Add the kernel driver Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 14/27] iommu/arm-smmu-v3: Support probing KVM emulated devices Mostafa Saleh
2025-11-28 16:56   ` Jason Gunthorpe
2025-12-12 15:53     ` Mostafa Saleh
2025-12-17 14:00       ` Jason Gunthorpe
2025-11-17 18:48 ` [PATCH v5 15/27] iommu/arm-smmu-v3-kvm: Create array for hyp SMMUv3 Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 16/27] iommu/arm-smmu-v3-kvm: Take over SMMUs Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 17/27] iommu/arm-smmu-v3-kvm: Probe SMMU HW Mostafa Saleh
2025-11-28 17:07   ` Jason Gunthorpe
2025-12-12 16:07     ` Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 18/27] iommu/arm-smmu-v3-kvm: Add MMIO emulation Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 19/27] iommu/arm-smmu-v3-kvm: Shadow the command queue Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 20/27] iommu/arm-smmu-v3-kvm: Add CMDQ functions Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 21/27] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 22/27] iommu/arm-smmu-v3-kvm: Shadow stream table Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 23/27] iommu/arm-smmu-v3-kvm: Shadow STEs Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 24/27] iommu/arm-smmu-v3-kvm: Emulate GBPA Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 25/27] iommu/arm-smmu-v3-kvm: Support io-pgtable Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 26/27] iommu/arm-smmu-v3-kvm: Shadow the CPU stage-2 page table Mostafa Saleh
2025-11-17 18:48 ` [PATCH v5 27/27] iommu/arm-smmu-v3-kvm: Enable nesting Mostafa Saleh
2025-11-28 17:12   ` Jason Gunthorpe
2025-12-12 16:15     ` Mostafa Saleh

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