From: Akhil P Oommen <akhilpo@oss.qualcomm.com>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Sean Paul <sean@poorly.run>, Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Jonathan Marek <jonathan@marek.ca>,
Jordan Crouse <jordan@cosmicpenguin.net>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Joerg Roedel <joro@8bytes.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Connor Abbott <cwabbott0@gmail.com>
Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
devicetree@vger.kernel.org,
Akhil P Oommen <akhilpo@oss.qualcomm.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Subject: [PATCH v4 08/22] drm/msm/adreno: Add MMU fault handler to adreno_gpu_func
Date: Tue, 18 Nov 2025 14:20:35 +0530 [thread overview]
Message-ID: <20251118-kaana-gpu-support-v4-8-86eeb8e93fb6@oss.qualcomm.com> (raw)
In-Reply-To: <20251118-kaana-gpu-support-v4-0-86eeb8e93fb6@oss.qualcomm.com>
Move MMU fault handler for each generation to adreno function list. This
will help to use common code for mmu pagefault handler registration between
a6x/a7x and a8x layer.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++++-
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 575f2f9d3b1d..9edd23d419ec 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2641,7 +2641,7 @@ static struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
adreno_gpu->uche_trap_base = 0x1fffffffff000ull;
msm_mmu_set_fault_handler(to_msm_vm(gpu->vm)->mmu, gpu,
- a6xx_fault_handler);
+ adreno_gpu->funcs->mmu_fault_handler);
ret = a6xx_calc_ubwc_config(adreno_gpu);
if (ret) {
@@ -2686,6 +2686,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = {
.init = a6xx_gpu_init,
.get_timestamp = a6xx_gmu_get_timestamp,
.bus_halt = a6xx_bus_clear_pending_transactions,
+ .mmu_fault_handler = a6xx_fault_handler,
};
const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
@@ -2717,6 +2718,7 @@ const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = {
.init = a6xx_gpu_init,
.get_timestamp = a6xx_get_timestamp,
.bus_halt = a6xx_bus_clear_pending_transactions,
+ .mmu_fault_handler = a6xx_fault_handler,
};
const struct adreno_gpu_funcs a7xx_gpu_funcs = {
@@ -2750,4 +2752,5 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
.init = a6xx_gpu_init,
.get_timestamp = a6xx_gmu_get_timestamp,
.bus_halt = a6xx_bus_clear_pending_transactions,
+ .mmu_fault_handler = a6xx_fault_handler,
};
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
index 08bb601b3bd3..922d2dee70fb 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -78,6 +78,7 @@ struct adreno_gpu_funcs {
struct msm_gpu *(*init)(struct drm_device *dev);
int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off);
+ int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data);
};
struct adreno_reglist {
--
2.51.0
next prev parent reply other threads:[~2025-11-18 8:52 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-18 8:50 [PATCH v4 00/22] drm/msm/adreno: Introduce Adreno 8xx family support Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 01/22] drm/msm/a6xx: Fix out of bound IO access in a6xx_get_gmu_registers Akhil P Oommen
2025-11-18 10:09 ` Konrad Dybcio
2025-11-18 8:50 ` [PATCH v4 02/22] drm/msm/a6xx: Flush LRZ cache before PT switch Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 03/22] drm/msm/a6xx: Fix the gemnoc workaround Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 04/22] drm/msm/a6xx: Skip dumping SCRATCH registers Akhil P Oommen
2025-11-18 12:15 ` Konrad Dybcio
2025-11-18 8:50 ` [PATCH v4 06/22] drm/msm/adreno: Move adreno_gpu_func to catalogue Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 07/22] drm/msm/adreno: Move gbif_halt() to adreno_gpu_func Akhil P Oommen
2025-11-18 8:50 ` Akhil P Oommen [this message]
2025-11-18 8:50 ` [PATCH v4 10/22] drm/msm/a6xx: Rebase GMU register offsets Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 11/22] drm/msm/a8xx: Add support for A8x GMU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 12/22] drm/msm/a6xx: Improve MX rail fallback in RPMH vote init Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 13/22] drm/msm/a6xx: Share dependency vote table with GMU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 14/22] drm/msm/adreno: Introduce A8x GPU Support Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 15/22] drm/msm/adreno: Support AQE engine Akhil P Oommen
2025-11-18 10:10 ` Konrad Dybcio
2025-11-18 15:56 ` Connor Abbott
2025-11-18 17:56 ` Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 16/22] drm/msm/a8xx: Add support for Adreno 840 GPU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 17/22] drm/msm/adreno: Do CX GBIF config before GMU start Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 18/22] drm/msm/a8xx: Add support for Adreno X2-85 GPU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 19/22] dt-bindings: arm-smmu: Add Kaanapali and Glymur GPU SMMU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 20/22] dt-bindings: display/msm/gmu: Add Adreno 840 GMU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 21/22] dt-bindings: display/msm/gmu: Add Adreno X2-85 GMU Akhil P Oommen
2025-11-18 8:50 ` [PATCH v4 22/22] drm/msm/a8xx: Add UBWC v6 support Akhil P Oommen
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