From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, kvm@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oupton@kernel.org>,
Zenghui Yu <yuzenghui@huawei.com>
Subject: [PATCH 1/5] KVM: arm64: Add routing/handling for GMID_EL1
Date: Thu, 20 Nov 2025 13:31:58 +0000 [thread overview]
Message-ID: <20251120133202.2037803-2-maz@kernel.org> (raw)
In-Reply-To: <20251120133202.2037803-1-maz@kernel.org>
HCR_EL2.TID5 is currently ignored by the trap routing infrastructure,
and we currently don't handle GMID_EL1 either (the only register trapped
by TID5).
Wire both the trap bit and a default UNDEF handler.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/emulate-nested.c | 8 ++++++++
arch/arm64/kvm/sys_regs.c | 1 +
2 files changed, 9 insertions(+)
diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
index 834f13fb1fb7d..616eb6ad68701 100644
--- a/arch/arm64/kvm/emulate-nested.c
+++ b/arch/arm64/kvm/emulate-nested.c
@@ -70,6 +70,7 @@ enum cgt_group_id {
CGT_HCR_ENSCXT,
CGT_HCR_TTLBIS,
CGT_HCR_TTLBOS,
+ CGT_HCR_TID5,
CGT_MDCR_TPMCR,
CGT_MDCR_TPM,
@@ -308,6 +309,12 @@ static const struct trap_bits coarse_trap_bits[] = {
.mask = HCR_TTLBOS,
.behaviour = BEHAVE_FORWARD_RW,
},
+ [CGT_HCR_TID5] = {
+ .index = HCR_EL2,
+ .value = HCR_TID5,
+ .mask = HCR_TID5,
+ .behaviour = BEHAVE_FORWARD_RW,
+ },
[CGT_MDCR_TPMCR] = {
.index = MDCR_EL2,
.value = MDCR_EL2_TPMCR,
@@ -665,6 +672,7 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = {
SR_TRAP(SYS_CCSIDR2_EL1, CGT_HCR_TID2_TID4),
SR_TRAP(SYS_CLIDR_EL1, CGT_HCR_TID2_TID4),
SR_TRAP(SYS_CSSELR_EL1, CGT_HCR_TID2_TID4),
+ SR_TRAP(SYS_GMID_EL1, CGT_HCR_TID5),
SR_RANGE_TRAP(SYS_ID_PFR0_EL1,
sys_reg(3, 0, 0, 7, 7), CGT_HCR_TID3),
SR_TRAP(SYS_ICC_SGI0R_EL1, CGT_HCR_IMO_FMO_ICH_HCR_TC),
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e67eb39ddc118..84e6f04220589 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -3397,6 +3397,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
.set_user = set_clidr, .val = ~CLIDR_EL1_RES0 },
{ SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
+ { SYS_DESC(SYS_GMID_EL1), undef_access },
{ SYS_DESC(SYS_SMIDR_EL1), undef_access },
IMPLEMENTATION_ID(AIDR_EL1, GENMASK_ULL(63, 0)),
{ SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
--
2.47.3
next prev parent reply other threads:[~2025-11-20 13:32 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-20 13:31 [PATCH 0/5] KVM: arm64: Add support for FEAT_IDST Marc Zyngier
2025-11-20 13:31 ` Marc Zyngier [this message]
2025-11-20 13:31 ` [PATCH 2/5] KVM: arm64: Force trap of GMID_EL1 when the guest doesn't have MTE Marc Zyngier
2025-11-20 14:34 ` Joey Gouly
2025-11-20 14:51 ` Marc Zyngier
2025-11-20 13:32 ` [PATCH 3/5] KVM: arm64: Add a generic synchronous exception injection primitive Marc Zyngier
2025-11-20 13:32 ` [PATCH 4/5] KVM: arm64: Report optional ID register traps with a 0x18 syndrome Marc Zyngier
2025-11-24 10:41 ` Ben Horgan
2025-11-24 11:48 ` Marc Zyngier
2025-11-20 13:32 ` [PATCH 5/5] KVM: arm64: selftests: Add a test for FEAT_IDST Marc Zyngier
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