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Sat, 22 Nov 2025 01:32:18 -0800 (PST) Date: Sat, 22 Nov 2025 09:32:04 +0000 Mime-Version: 1.0 X-B4-Tracking: v=1; b=H4sIABWDIWkC/03MQQ7CIBCF4as0s5YGsBVx5T2MiwpTSkKZZqhG0 /TuElfmrb7F+zcoyBELXJoNGF+xRMoV50MDbhpyQBF9NWipe6W0Fo7yypQSslDaPqT3vRlMB/W wMI7x/Yvd7tUj0yzWiXH4Sygr7dF0ttW27iSUYPqkJ10DUUjYOpph37/ydFcomAAAAA== X-Change-Id: 20251122-controller-129b0dd57a74 X-Developer-Key: i=royluo@google.com; a=ed25519; pk=nTq1n8WcJActRWe1s8jdcy+TzpTK4a+IYRCIWvQfq5k= X-Developer-Signature: v=1; a=ed25519-sha256; t=1763803936; l=3975; i=royluo@google.com; s=20251120; h=from:subject:message-id; bh=oJgoRCcsl7Ld3GyB5zmfSn3D/dubRzVSvimNvflfqL8=; b=eXkpcKtxNEknJRDqkFeDEcWxN1Qv5VDUMbjbIGCYpqoA3dLbDO6Nf86SkmHY4nPpnk9jNbl+8 KMHTxP0/FLGBBgaDMmnRJpARGwDDNL6MWqFuzfqTC8I3+6/h6b5LBBg X-Mailer: b4 0.14.2 Message-ID: <20251122-controller-v8-0-e7562e0df658@google.com> Subject: [PATCH v8 0/2] Add Google Tensor SoC USB controller support From: Roy Luo To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter Griffin , "=?utf-8?q?Andr=C3=A9_Draszik?=" , Tudor Ambarus , Thinh Nguyen , Philipp Zabel Cc: Badhri Jagan Sridharan , Doug Anderson , linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Joy Chakraborty , Naveen Kumar , Roy Luo , Krzysztof Kozlowski Content-Type: text/plain; charset="utf-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251122_013219_668787_DCA45D5B X-CRM114-Status: GOOD ( 15.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series introduces USB controller support for the Google Tensor G5 SoC (codename: Laguna), a new generation of Google silicon first launched with Pixel 10 devices. The Tensor G5 represents a significant architectural overhaul compared to previous Tensor generations (e.g., gs101), which were based on Samsung Exynos IP. Although the G5 still utilizes Synopsys IP for the USB components, the custom top-level integration introduces a completely new design for clock, reset scheme, register interfaces and programming sequence, necessitating new drivers and device tree bindings. The USB subsystem on Tensor G5 integrates a Synopsys DWC3 USB 3.1 DRD-Single Port controller with hibernation support, and a custom PHY block comprising Synopsys eUSB2 and USB 3.2/DP combo PHYs. The PHY support is sent as a separate patch series. Co-developed-by: Joy Chakraborty Signed-off-by: Joy Chakraborty Co-developed-by: Naveen Kumar Signed-off-by: Naveen Kumar Signed-off-by: Roy Luo --- Changes in v8: - Add COMPILE_TEST to dependencies for build coverage. - Drop redundant default n in Kconfig. - Update Kconfig help text to explicitly state the module name. - Use container_of_const() in the to_dwc3_google() macro for type safety. Link to v7: https://lore.kernel.org/linux-usb/20251119093749.292926-1-royluo@google.com Changes in v7: - Follow driver naming convention and rename the driver as "dwc3-google". Link to v6: https://lore.kernel.org/linux-usb/20251112123257.3755489-1-royluo@google.com Changes in v6: - Use "lga" as SoC name instead of "gs5" to align with Tensor G5 device tree https://lore.kernel.org/lkml/20251111192422.4180216-1-dianders@chromium.org Link to v5: https://lore.kernel.org/linux-usb/20251111130624.3069704-1-royluo@google.com Changes in v5: - Use syscon to access host_cfg and usbint_cfg MMIO space per discussion in https://lore.kernel.org/linux-phy/89733ddf-8af3-42d0-b6e5-20b7a4ef588c@kernel.org - Make warn logs in dwc3_google_resume_irq() dev_dbg. Link to v4: https://lore.kernel.org/linux-usb/20251017233459.2409975-1-royluo@google.com Changes in v4: - Separate controller and phy changes into two distinct patch series. - Rename dwc3 core interrupt as "core". - Remove u2phy_apb clk/reset (moved to PHY) - Configure usb2only mode when usb3 phy is not present. - Adopt pm_ptr PM macros to fix build warnings. Link to v3: https://lore.kernel.org/linux-usb/20251010201607.1190967-1-royluo@google.com Changes in v3: - Align binding file name with the compatible string - Simplify the compatible property in binding to a single const value. - Add descriptive comments and use item list in binding. - Rename binding entries for clarity and brevity. Link to v2: https://lore.kernel.org/linux-usb/20251008060000.3136021-1-royluo@google.com Changes in v2: - Reorder patches to present bindings first. - Update dt binding compatible strings to be SoC-specific (google,gs5-*). - Better describe the hardware in dt binding commit messages and descriptions. - Adjust PHY driver commit subjects to use correct prefixes ("phy:"). - Move PHY driver from a subdirectory to drivers/phy/. Link to v1: https://lore.kernel.org/linux-usb/20251006232125.1833979-1-royluo@google.com/ --- Roy Luo (2): dt-bindings: usb: dwc3: Add Google Tensor G5 DWC3 usb: dwc3: Add Google Tensor SoC DWC3 glue driver .../devicetree/bindings/usb/google,lga-dwc3.yaml | 140 +++++ drivers/usb/dwc3/Kconfig | 13 + drivers/usb/dwc3/Makefile | 1 + drivers/usb/dwc3/dwc3-google.c | 628 +++++++++++++++++++++ 4 files changed, 782 insertions(+) --- base-commit: 8b690556d8fe074b4f9835075050fba3fb180e93 change-id: 20251122-controller-129b0dd57a74 Best regards, -- Roy Luo