[PATCH v3 3/3] arm64: dts: cix: add support for cix sky1 resets

Gary Yang
2025-11-24T06:32:58Z

There are two reset conctrollers on Cix Sky1 Soc.
One is located in S0 domain, and the other is located
in S5 domain.

Signed-off-by: Gary Yang <gary.yang@cixtech.com>
---
arch/arm64/boot/dts/cix/sky1.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index d21387224e79..72ebffe05ef7 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -348,6 +348,12 @@ i3c1: i3c@4100000 {
status = "disabled";
};

+ src_fch: reset-controller@4160008 {
+ compatible = "cix,sky1-rst-fch";
+ reg = <0x0 0x04160008 0x0 0xc>;
+ #reset-cells = <1>;
+ };
+
iomuxc: pinctrl@4170000 {
compatible = "cix,sky1-iomuxc";
reg = <0x0 0x04170000 0x0 0x1000>;
@@ -568,6 +574,14 @@ ppi_partition1: interrupt-partition-1 {
};
};

+ src: reset-controller@16000304 {
+ compatible = "cix,sky1-rst";
+ reg = <0x0 0x16000304 0x0 0xc>,
+ <0x0 0x16000400 0x0 0x10>,
+ <0x0 0x16000800 0x0 0x8>;
+ #reset-cells = <1>;
+ };
+
iomuxc_s5: pinctrl@16007000 {
compatible = "cix,sky1-iomuxc-s5";
reg = <0x0 0x16007000 0x0 0x1000>;
--
2.49.0