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charset=us-ascii Content-Disposition: inline In-Reply-To: <20251118202210.GA2586610@bhelgaas> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 18, 2025 at 02:22:13PM -0600, Bjorn Helgaas wrote: > On Wed, Nov 12, 2025 at 11:21:07PM +0530, Manivannan Sadhasivam wrote: > > On Wed, Nov 12, 2025 at 09:22:36AM +0100, Niklas Cassel wrote: > > > On Tue, Nov 11, 2025 at 04:16:08PM -0600, Bjorn Helgaas wrote: > > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > > > @@ -1060,6 +1060,8 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > > > > PCI_COMMAND_MASTER | PCI_COMMAND_SERR; > > > > dw_pcie_writel_dbi(pci, PCI_COMMAND, val); > > > > > > > > + dw_pcie_config_l1ss(pci); > > > > > --- a/drivers/pci/controller/dwc/pcie-qcom.c > > > > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > > > > @@ -1067,6 +1067,8 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) > > > > val &= ~REQ_NOT_ENTR_L1; > > > > writel(val, pcie->parf + PARF_PM_CTRL); > > > > > > > > + pci->l1ss_support = true; > > > > + > > > > val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > > > > val |= EN; > > > > writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > > > > > > While it seems like ops_2_7_0 is the only type that explicitly does a > > > register write to enable L1ss, other versions might have the register > > > as enabled by default, so it would be nice if Mani could confirm exactly > > > which versions that should set l1ss_support = true. > > > > > > > Yes, on the rest of the platforms, this bit is supposed to be enabled by > > default. AFAIK, all Qcom platforms should support L1SS, atleast the > > non-IPQ/APQ ones. > > > > We should set it for below cfgs: > > > > cfg_fw_managed > > cfg_sc8280xp > > cfg_1_34_0 > > cfg_1_9_0 > > cfg_2_7_0 > > Except for cfg_fw_managed, the above are all covered by > qcom_pcie_init_2_7_0(), either via ops_2_7_0, ops_1_9_0, or > ops_1_21_0. > > cfg_fw_managed is harder because we don't use dw_pcie_host_init() or > dw_pcie_setup_rc(). > > We do allocate a struct dw_pcie (where l1ss_support is) in > qcom_pcie_ecam_host_init(), but only so we can call > dw_pcie_msi_host_init() and dw_pcie_msi_init(). I'm just back from vacation so might be forgetting something, but I think cfg_fw_managed is OK here because in that case we never call dw_pcie_host_init(), so we never call dw_pcie_setup_rc() where dw_pcie_hide_unsupported_l1ss(). So the L1SS cap should remain untouched and presumably advertises the L1SS support we want for cfg_fw_managed. Bjorn