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X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Anirudh Rayabharam To receive hypervisor intercept interrupts on arm64 under MSHV, the parent partition must allocate an interrupt in the SGI or PPI range and program it into the SYNIC. Currently, Linux provides no mechanism for drivers to dynamically allocate either SGIs or PPIs. SGIs are allocated exclusively by the GIC driver for use by the SMP subsystem as IPIs, while PPIs must be described in firmware (DT or ACPI), leaving the OS unable to allocate new ones at runtime. This series introduces support for MSHV by extending the GICv3 driver to reserve one additional SGI specifically for use by the MSHV driver. The reserved SGI is then used by the MSHV driver to program the SYNIC and receive hypervisor intercept notifications. This mechanism allows the MSHV driver to function correctly on arm64 without requiring firmware changes or altering the semantics of PPIs, while keeping the SGI allocation model self-contained within the GIC driver. Anirudh Rayabharam (Microsoft) (3): arm64: hyperv: move hyperv detection earlier in boot irqchip/gic-v3: allocate one SGI for MSHV mshv: add support for VMEXIT interrupts on aarch64 arch/arm64/hyperv/mshyperv.c | 31 +++++++++++++--- arch/arm64/include/asm/mshyperv.h | 10 ++++++ arch/arm64/kernel/setup.c | 6 ++++ drivers/hv/mshv_root_main.c | 59 +++++++++++++++++++++++++++++++ drivers/hv/mshv_synic.c | 15 ++++---- drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++-- include/asm-generic/mshyperv.h | 3 ++ 7 files changed, 139 insertions(+), 14 deletions(-) -- 2.34.1