[PATCH] arm64: dts: morello: Add CMN PMU

[PATCH] arm64: dts: morello: Add CMN PMU

[Robin Murphy]

Although CMN-Skeena is mildly modified for the Morello hardware
architecture, it still identifies itself as CMN-600 r3p1. Since
there are also no documented changes to its PMU functionality,
we can make the PMU accessible via the standard CMN-600 binding.
In general, PMU registers are non-functional on CMN Fast Models,
so this is only meaningful for the real SDP hardware.

Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
 arch/arm64/boot/dts/arm/morello-sdp.dts | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts
index cee49dee7571..42c85f450fa9 100644
--- a/arch/arm64/boot/dts/arm/morello-sdp.dts
+++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
@@ -108,6 +108,13 @@ smmu_pcie: iommu@4f400000 {
 		dma-coherent;
 	};
 
+	pmu@50000000 {
+		compatible = "arm,cmn-600";
+		reg = <0x0 0x50000000 0x0 0x4000000>;
+		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+		arm,root-node = <0x804000>;
+	};
+
 	pcie_ctlr: pcie@28c0000000 {
 		device_type = "pci";
 		compatible = "pci-host-ecam-generic";
-- 
2.39.2.101.g768bb238c484.dirty

Re: [PATCH] arm64: dts: morello: Add CMN PMU

[Robin Murphy]

[ Trying to catch up with loose ends... ]

On 2025-05-27 1:55 pm, Robin Murphy wrote:
> Although CMN-Skeena is mildly modified for the Morello hardware
> architecture, it still identifies itself as CMN-600 r3p1. Since
> there are also no documented changes to its PMU functionality,
> we can make the PMU accessible via the standard CMN-600 binding.
> In general, PMU registers are non-functional on CMN Fast Models,
> so this is only meaningful for the real SDP hardware.

Vincenzo, Sudeep, any opinion on this? I believe it was considered 
useful by at least the one person who asked me about it :)

Thanks,
Robin.

> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
> ---
>   arch/arm64/boot/dts/arm/morello-sdp.dts | 7 +++++++
>   1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts
> index cee49dee7571..42c85f450fa9 100644
> --- a/arch/arm64/boot/dts/arm/morello-sdp.dts
> +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
> @@ -108,6 +108,13 @@ smmu_pcie: iommu@4f400000 {
>   		dma-coherent;
>   	};
>   
> +	pmu@50000000 {
> +		compatible = "arm,cmn-600";
> +		reg = <0x0 0x50000000 0x0 0x4000000>;
> +		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> +		arm,root-node = <0x804000>;
> +	};
> +
>   	pcie_ctlr: pcie@28c0000000 {
>   		device_type = "pci";
>   		compatible = "pci-host-ecam-generic";

Re: [PATCH] arm64: dts: morello: Add CMN PMU

[Vincenzo Frascino]

On 27/05/2025 13:55, Robin Murphy wrote:
> Although CMN-Skeena is mildly modified for the Morello hardware
> architecture, it still identifies itself as CMN-600 r3p1. Since
> there are also no documented changes to its PMU functionality,
> we can make the PMU accessible via the standard CMN-600 binding.
> In general, PMU registers are non-functional on CMN Fast Models,
> so this is only meaningful for the real SDP hardware.
> 
> Signed-off-by: Robin Murphy <robin.murphy@arm.com>

Fine by me.

Acked-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

> ---
>  arch/arm64/boot/dts/arm/morello-sdp.dts | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/arm/morello-sdp.dts
> index cee49dee7571..42c85f450fa9 100644
> --- a/arch/arm64/boot/dts/arm/morello-sdp.dts
> +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
> @@ -108,6 +108,13 @@ smmu_pcie: iommu@4f400000 {
>  		dma-coherent;
>  	};
>  
> +	pmu@50000000 {
> +		compatible = "arm,cmn-600";
> +		reg = <0x0 0x50000000 0x0 0x4000000>;
> +		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
> +		arm,root-node = <0x804000>;
> +	};
> +
>  	pcie_ctlr: pcie@28c0000000 {
>  		device_type = "pci";
>  		compatible = "pci-host-ecam-generic";

-- 
Regards,
Vincenzo

Re: [PATCH] arm64: dts: morello: Add CMN PMU

[Vincenzo Frascino]

Hi Robin,

On 24/11/2025 16:35, Robin Murphy wrote:
> [ Trying to catch up with loose ends... ]
> 
> On 2025-05-27 1:55 pm, Robin Murphy wrote:
>> Although CMN-Skeena is mildly modified for the Morello hardware
>> architecture, it still identifies itself as CMN-600 r3p1. Since
>> there are also no documented changes to its PMU functionality,
>> we can make the PMU accessible via the standard CMN-600 binding.
>> In general, PMU registers are non-functional on CMN Fast Models,
>> so this is only meaningful for the real SDP hardware.
> 
> Vincenzo, Sudeep, any opinion on this? I believe it was considered useful by at
> least the one person who asked me about it :)
> 

Sorry, I missed your patch. Just acked it.

> Thanks,
> Robin.
> 
>>
>> Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>> ---
>>   arch/arm64/boot/dts/arm/morello-sdp.dts | 7 +++++++
>>   1 file changed, 7 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/
>> arm/morello-sdp.dts
>> index cee49dee7571..42c85f450fa9 100644
>> --- a/arch/arm64/boot/dts/arm/morello-sdp.dts
>> +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts
>> @@ -108,6 +108,13 @@ smmu_pcie: iommu@4f400000 {
>>           dma-coherent;
>>       };
>>   +    pmu@50000000 {
>> +        compatible = "arm,cmn-600";
>> +        reg = <0x0 0x50000000 0x0 0x4000000>;
>> +        interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
>> +        arm,root-node = <0x804000>;
>> +    };
>> +
>>       pcie_ctlr: pcie@28c0000000 {
>>           device_type = "pci";
>>           compatible = "pci-host-ecam-generic";
> 

-- 
Regards,
Vincenzo

Re: [PATCH] arm64: dts: morello: Add CMN PMU

[Sudeep Holla]

On Mon, Nov 24, 2025 at 04:35:39PM +0000, Robin Murphy wrote:
> [ Trying to catch up with loose ends... ]
> 
> On 2025-05-27 1:55 pm, Robin Murphy wrote:
> > Although CMN-Skeena is mildly modified for the Morello hardware
> > architecture, it still identifies itself as CMN-600 r3p1. Since
> > there are also no documented changes to its PMU functionality,
> > we can make the PMU accessible via the standard CMN-600 binding.
> > In general, PMU registers are non-functional on CMN Fast Models,
> > so this is only meaningful for the real SDP hardware.
> 
> Vincenzo, Sudeep, any opinion on this? I believe it was considered useful by
> at least the one person who asked me about it :)
>

Sorry for missing it earlier and even this almost 😉. Anyways too late for
v6.19, will pick it up for following merge window.

-- 
Regards,
Sudeep